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AD9510/PCB Scheda tecnica(PDF) 9 Page - Analog Devices

Il numero della parte AD9510/PCB
Spiegazioni elettronici  1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs
PDF  60 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
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AD9510/PCB Scheda tecnica(HTML) 9 Page - Analog Devices

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AD9510
Rev. A | Page 9 of 60
CLOCK OUTPUT PHASE NOISE
Table 5.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CLK1-TO-LVPECL ADDITIVE PHASE NOISE
Distribution Section only; does not
include PLL or external VCO/VCXO
CLK1 = 622.08 MHz, OUT = 622.08 MHz
Input slew rate > 1 V/ns
Divide Ratio = 1
@ 10 Hz Offset
−125
dBc/Hz
@ 100 Hz Offset
−132
dBc/Hz
@ 1 kHz Offset
−140
dBc/Hz
@ 10 kHz Offset
−148
dBc/Hz
@ 100 kHz Offset
−153
dBc/Hz
>1 MHz Offset
−154
dBc/Hz
CLK1 = 622.08 MHz, OUT = 155.52 MHz
Divide Ratio = 4
@ 10 Hz Offset
−128
dBc/Hz
@ 100 Hz Offset
−140
dBc/Hz
@ 1 kHz Offset
−148
dBc/Hz
@ 10 kHz Offset
−155
dBc/Hz
@ 100 kHz Offset
−161
dBc/Hz
>1 MHz Offset
−161
dBc/Hz
CLK1 = 622.08 MHz, OUT = 38.88 MHz
Divide Ratio = 16
@ 10 Hz Offset
−135
dBc/Hz
@ 100 Hz Offset
−145
dBc/Hz
@ 1 kHz Offset
−158
dBc/Hz
@ 10 kHz Offset
−165
dBc/Hz
@ 100 kHz Offset
−165
dBc/Hz
>1 MHz Offset
−166
dBc/Hz
CLK1 = 491.52 MHz, OUT = 61.44 MHz
Divide Ratio = 8
@ 10 Hz Offset
−131
dBc/Hz
@ 100 Hz Offset
−142
dBc/Hz
@ 1 kHz Offset
−153
dBc/Hz
@ 10 kHz Offset
−160
dBc/Hz
@ 100 kHz Offset
−165
dBc/Hz
> 1 MHz Offset
−165
dBc/Hz
CLK1 = 491.52 MHz, OUT = 245.76 MHz
Divide Ratio = 2
@ 10 Hz Offset
−125
dBc/Hz
@ 100 Hz Offset
−132
dBc/Hz
@ 1 kHz Offset
−140
dBc/Hz
@ 10 kHz Offset
−151
dBc/Hz
@ 100 kHz Offset
−157
dBc/Hz
>1 MHz Offset
−158
dBc/Hz
CLK1 = 245.76 MHz, OUT = 61.44 MHz
Divide Ratio = 4
@ 10 Hz Offset
−138
dBc/Hz
@ 100 Hz Offset
−144
dBc/Hz
@ 1 kHz Offset
−154
dBc/Hz
@ 10 kHz Offset
−163
dBc/Hz
@ 100 kHz Offset
−164
dBc/Hz
>1 MHz Offset
−165
dBc/Hz



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