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AD9510/PCB Scheda tecnica(PDF) 20 Page - Analog Devices

Il numero della parte AD9510/PCB
Spiegazioni elettronici  1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs
PDF  60 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
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AD9510
Rev. A | Page 20 of 60
Table 13. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
REFIN
PLL Reference Input.
2
REFINB
Complementary PLL Reference Input.
3, 7, 8, 12, 22,
27, 32, 49, 50,
55, 62
GND
Ground.
4, 9, 13, 23, 26,
30, 31, 33, 36,
37, 40, 41, 44,
45, 48, 51, 52,
56, 59, 60, 64
VS
Power Supply (3.3 V) VS.
5
VCP
Charge Pump Power Supply VCPS. It should be greater than or equal to VS. VCPS may be set as high as 5.5 V
for VCOs requiring extended tuning range.
6
CP
Charge Pump Output.
10
CLK2
Clock Input Used to Connect External VCO/VCXO to Feedback Divider, N. CLK2 also drives the distribution
section of the chip and may be used as a generic clock input when PLL is not used.
11
CLK2B
Complementary Clock Input Used in Conjunction with CLK2.
14
CLK1
Clock Input that Drives Distribution Section of the Chip.
15
CLK1B
Complementary Clock Input Used in Conjunction with CLK1.
16
FUNCTION
Multipurpose Input May Be Programmed as a Reset (RESETB), Sync (SYNCB), or Power-Down (PDB) Pin.
This pin is internally pulled down by a 30 kΩ resistor. If this pin is left NC, the part is in reset by default.
To avoid this, connect this pin to VS with a 1 kΩ resistor.
17
STATUS
Output Used to Monitor PLL Status and Sync Status.
18
SCLK
Serial Data Clock.
19
SDIO
Serial Data I/O.
20
SDO
Serial Data Output.
21
CSB
Serial Port Chip Select.
24
OUT7B
Complementary LVDS/Inverted CMOS Output.
25
OUT7
LVDS/CMOS Output.
28
OUT3B
Complementary LVPECL Output.
29
OUT3
LVPECL Output.
34
OUT2B
Complementary LVPECL Output.
35
OUT2
LVPECL Output.
38
OUT6B
Complementary LVDS/Inverted CMOS Output. OUT6 includes a delay block.
39
OUT6
LVDS/CMOS Output. OUT6 includes a delay block.
42
OUT5B
Complementary LVDS/Inverted CMOS Output. OUT5 includes a delay block.
43
OUT5
LVDS/CMOS Output. OUT5 includes a delay block.
46
OUT4B
Complementary LVDS/Inverted CMOS Output.
47
OUT4
LVDS/CMOS Output.
53
OUT1B
Complementary LVPECL Output.
54
OUT1
LVPECL Output.
57
OUT0B
Complementary LVPECL Output.
58
OUT0
LVPECL Output.
61
RSET
Current Set Resistor to Ground. Nominal value = 4.12 kΩ.
63
CPRSET
Charge Pump Current Set Resistor to Ground. Nominal value = 5.1 kΩ.
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to
function properly, the paddle must be attached to ground, GND.



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