AD9510SLASHPCB datasheet(13/60 Pages) AD

13 / 60 page

AD9510

Rev. A | Page 13 of 60

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLK1 = 400 MHz

395

fs rms

Calculated from SNR of ADC method;

FC = 100 MHz with AIN = 170 MHz

LVDS (OUT4, OUT7) = 100 MHz

Divide Ratio = 4

All Other LVDS = 50 MHz

Interferer(s)

All LVPECL = 50 MHz

Interferer(s)

CLK1 = 400 MHz

395

fs rms

Calculated from SNR of ADC method;

FC = 100 MHz with AIN = 170 MHz

LVDS (OUT5, OUT6) = 100 MHz

Divide Ratio = 4

All Other LVDS = 50 MHz

Interferer(s)

All LVPECL = 50 MHz

Interferer(s)

CLK1 = 400 MHz

367

fs rms

Calculated from SNR of ADC method;

FC = 100 MHz with AIN = 170 MHz

LVDS (OUT4, OUT7) = 100 MHz

Divide Ratio = 4

All Other CMOS = 50 MHz (B Outputs Off)

Interferer(s)

All LVPECL = 50 MHz

Interferer(s)

CLK1 = 400 MHz

367

fs rms

Calculated from SNR of ADC method;

FC = 100 MHz with AIN = 170 MHz

LVDS (OUT5, OUT6) = 100 MHz

Divide Ratio = 4

All Other CMOS = 50 MHz (B Outputs Off)

Interferer(s)

All LVPECL = 50 MHz

Interferer(s)

CLK1 = 400 MHz

548

fs rms

Calculated from SNR of ADC method;

FC = 100 MHz with AIN = 170 MHz

LVDS (OUT4, OUT7) = 100 MHz

Divide Ratio = 4

All Other CMOS = 50 MHz (B Outputs On)

Interferer(s)

All LVPECL = 50 MHz

Interferer(s)

CLK1 = 400 MHz

548

fs rms

Calculated from SNR of ADC method;

FC = 100 MHz with AIN = 170 MHz

LVDS (OUT5, OUT6) = 100 MHz

Divide Ratio = 4

All Other CMOS = 50 MHz (B Outputs On)

Interferer(s)

All LVPECL = 50 MHz

Interferer(s)

CMOS OUTPUT ADDITIVE TIME JITTER

Distribution Section only;

does not include PLL or external VCO/VCXO

CLK1 = 400 MHz

275

fs rms

Calculated from SNR of ADC method;

FC = 100 MHz with AIN = 170 MHz

Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On)

Divide Ratio = 4

CLK1 = 400 MHz

400

fs rms

Calculated from SNR of ADC method;

FC = 100 MHz with AIN = 170 MHz

Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On)

Divide Ratio = 4

All LVPECL = 50 MHz

Interferer(s)

All Other LVDS = 50 MHz

Interferer(s)

CLK1 = 400 MHz

374

fs rms

Calculated from SNR of ADC method;

FC = 100 MHz with AIN = 170 MHz

Any CMOS (OUT4 to OUT7) = 100 MHz (B Output On)

Divide Ratio = 4

All LVPECL = 50 MHz

Interferer(s)

All Other CMOS = 50 MHz (B Output Off)

Interferer(s)

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