AD9510SLASHPCB datasheet(15/60 Pages) AD

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AD9510

Rev. A | Page 15 of 60

SERIAL CONTROL PORT

Table 8.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CSB, SCLK (INPUTS)

CSB and SCLK have 30 kΩ

internal pull-down resistors

Input Logic 1 Voltage

2.0

Input Logic 0 Voltage

0.8

Input Logic 1 Current

110

μA

Input Logic 0 Current

μA

Input Capacitance

SDIO (WHEN INPUT)

Input Logic 1 Voltage

2.0

Input Logic 0 Voltage

0.8

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage

2.7

Output Logic 0 Voltage

0.4

TIMING

Clock Rate (SCLK, 1/tSCLK)

MHz

Pulse Width High, tPWH

Pulse Width Low, tPWL

SDIO to SCLK Setup, tDS

SCLK to SDIO Hold, tDH

SCLK to Valid SDIO and SDO, tDV

CSB to SCLK Setup and Hold, tS, tH

CSB Minimum Pulse Width High, tPWH

FUNCTION PIN

Table 9.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

INPUT CHARACTERISTICS

The FUNCTION pin has a 30 kΩ internal pull-down resistor.

This pin should normally be held high. Do not leave NC.

Logic 1 Voltage

2.0

Logic 0 Voltage

0.8

Logic 1 Current

110

μA

Logic 0 Current

μA

Capacitance

RESET TIMING

Pulse Width Low

SYNC TIMING

Pulse Width Low

1.5

High speed clock cycles

High speed clock is CLK1 or CLK2,

whichever is being used for distribution

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