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CC1010-RTR1 Scheda tecnica(PDF) 129 Page - Texas Instruments |
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CC1010-RTR1 Scheda tecnica(HTML) 129 Page - Texas Instruments |
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129 / 152 page  CC1010 SWRS047 Page 129 of 152 18. Reserved registers and test registers The CC1010 contains a few registers intended for test purposes only. Normally these registers should not be written to. The FSHAPEn, FSDELAY and FSCTRL registers are reserved for future use. A separate reset signal for the PLL is available in FSCTRL.FS_RESET_N. This will reset the frequency divider part of the PLL. The reset is active when a zero is written, and a one must be written for the reset to be released. FSCTRL.EXT_FILTER can be set in order to use an external PLL loop filter. However, this is not recommended in a normal application. The PRESCALER register controls the prescaler current, and should always be set to 0x00 (which is the reset state). The TESTMUX register is not needed for normal operation of CC1010, but is included here for completeness. TESTMUX should always be set to 0x00. TESTMUX P0.2 P0.1 P0.0 0000 Normal operation Normal operation Normal operation 0001 CLK_REF CLK_PHASE_DET_OUT MODEM_TX_OUT 0010 LOCK_DET_CONTINUOUS LOCK_DET_INSTANT ANALOG_WINDOW_SYNC 0011 SER_PAR_IRQ TIMER2_IRQ TIMER3_IRQ 0100 RTC_IRQ ADC_IRQ DES_IRQ 0101 ANALOG_ALARM_H ANALOG_ALARM_L CAL_DIG_COMPLETE 0110 MODEM_BIT_CLK MODEM_RX_DATA ANALOG_IF_OUT 0111 MODEM_BIT_CLK MODEM_TX_DATA MODEM_TX_OUT 1000 ADC_SAR_ADCCLK_EN ANALOG_COMP ADC_SAR_EOC 1001 CLK_RTC RTC_IRQ CLK_UC 1010 DES_DEBUG_0 1011 DES_DEBUG_1 1100 DES_DEBUG_2 1101 DES_DEBUG_3 1110 FLASH_WRITE_IRQ 1111 CAL_DIG_COMPLETE Table 39. TESTMUX modes FSHAPEn (0xF1 - 0xF7), n ∈1..7 - Frequency Shaping Register n Bit Name R/W Reset value Description 7:5 - R0 0x00 Reserved, read as 0 4:0 FSHAPEn (4:0) R/W 0xXX Reserved for future use. FSDELAY (0xE9) - Frequency Shaping Delay Control Register Bit Name R/W Reset value Description 7:0 FSDELAY (7:0) R/W 0x2F Reserved for future use. |
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