TPS25751D datasheet(43/89 Pages) TI1

43 / 89 page

Data Line

Change

SDA

SCL

Figure 8-28. I2C Bit Transfer

SCL from

Controller

Figure 8-29. I2C Acknowledgment

8.3.11.1.1 I2C Clock Stretching

The TPS25751 features clock stretching for the I2C protocol. The TPS25751 target I2C port can hold the clock

line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data. The

controller communicating with the target must not finish the transmission of the current bit and must wait until the

clock line actually goes high. When the target is clock stretching, the clock line remains low.

The controller must wait until it observes the clock line transitioning high plus an additional minimum time (4 μs

for standard 100-kbps I2C) before pulling the clock low again.

Any clock pulse can be stretched but typically it is the interval before or after the acknowledgment bit.

8.3.11.1.2 I2C Address Setting

The I2C controller must only use I2Ct_SCL/SDA for loading a patch bundle.

Once the boot process is complete, the port has a unique target address on the I2Ct_SCL/SDA bus as selected

by the ADCINx pins.

Table 8-5. I2C Default Target Address for I2Ct_SCL/SDA.

I2C ADDRESS INDEX

(DECODED FROM ADCIN1

AND ADCIN2)(1)

TARGET ADDRESS

AVAILABLE

DURING BOOT

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

R/W

Yes

R/W

Yes

R/W

Yes

R/W

Yes

(1)

See Pin Strapping to Configure Default Behavior details about ADCIN1 and ADCIN2 decoding.

8.3.11.1.3 Unique Address Interface

The Unique Address Interface allows for complex interaction between an I2C controller and a single TPS25751.

The I2C target sub-address is used to receive or respond to Host Interface protocol commands. Figure 8-30 and

Figure 8-31 show the write and read protocol for the I2C target interface, and a key is included in Figure 8-32

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TPS25751

SLVSH93 – OCTOBER 2023

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