TPS25751D datasheet(65/89 Pages) TI1

65 / 89 page

The decoupling capacitors for LDO_3V3, LDO_1V5, and VIN_3V3 (C15, C16, and C17 respectively) need to

be placed as close as possible to TPS25751D device for optimal performance. For this example to minimize

solution size, the decoupling capacitors are placed on the bottom layer with their ground pads directly

underneath the ground pad of TPS25751D. Use a maximum of one via per pin from TPS25751D to the

decoupling capacitors if placed on a different layer. Use a minimum of 10mil trace width to route these three

traces, preferably with 16mil trace width if possible.

CC1 (pin 28) and CC2 (pin 29)

CC1 (C11) and CC2 (C10) capacitors need to be placed as close as possible to their respective pins and on the

same layer as the TPS25751D device. When routing the CCx traces, DO NOT via to another layer in between

the CCx pins of the TPS25751D to the CCx capacitors. Check to make sure the CCx capacitors are not place

outside the CC trace creating an antenna, instead have the traces pass directly through the CCx capacitor pads

as shown in the example layout (refer to figure 10-14 ). Use a minimum of 10mil trace width to ensure Vconn

support (5V/0.6A).

9.4.1.2.2.2 TPS25751D PP5V

The 10uF decoupling capacitor (C9) need to be placed as close as possible to the PP5V pins of TPS25751D.

DO NOT use traces for PP5V. The PP5V power plane needs to be sized to support up to 3.6A (up to 3A for

sourcing, 600mA for Vconn). When connecting the PP5V pins (pins 34 and 35) to the 5V power plane, use a

minimum of 4 vias in parallel and close to the device to improve current sharing. Minimize the bottle necks cause

by other vias or traces, large bottle necks reduces the efficiency of the power plane.

The bulk capacitors (C6, C7, and C8) represent capacitances from the system 5V rail, these are placed further

away from TPS25751D on the same PP5V power plane. Refer to figure 10-14 and figure 10-15 for placement

and trace reference.

9.4.1.2.2.3 TPS25751D PPHV

Place the PPHV decoupling capacitors (C12, C13, and C14) as close as possible to TPS25751D, these do not

need to be on the same layer as the device. The PPHV power plane needs to be sized to support up to 5A

of current. When connecting the PPHV plane to a different layer, use a minimum of 6 vias in parallel per layer

change. It is highly recommended to have more than 6 vias if possible for layer change to improve current

sharing and efficiency.

9.4.1.2.2.4 TPS25751D VBUS

VBUS (pins 32 and 33) and VBUS_IN (pins 23, 24, and 25)

Place the VBUS decoupling capacitor (C1) as close as possible to TPS25751D, the capacitor does not need to

be on the same layer as the device. The VBUS power plane need to be sized to support up to 5A of current if

100W application is required. When connecting the VBUS pins (pins 32 and 33) plane to a different layer, use

a minimum of 3 vias per layer change. When connecting the VBUS_IN pins (pins 23, 24, and 25) plane to a

different layer, use a minimum of 6 vias per layer change. Refer to figure 10-14 and figure 10-15 for capacitors

and via placement.

At the Type-C port/connector, it is recommended to use minimum of 6 vias from the connector VBUS pins for

layer changes. Place the 10nF caps (C2, C3, C4, and C5) and the 22V TVS diode (U2) as close as possible to

the connector VBUS pins as shown in figure 10-15.

When routing the VBUS power plane from the Type-C connector to the TPS25751D VBUS pins, minimize bottle

necks caused by other vias and traces to improve current flow. The example layout shown in figure 10-17 uses

an internal layer to route the VBUS plane from the connector to TPS25751D.

9.4.1.2.2.5 TPS25751D I/O (I2C, ADCINs, GPIOs)

I2C, ADCIN1/2, and GPIO pins

Fan these traces out from the TPS25751D, use vias to connect the net to a routing layer if needed. For these

nets, use 4mil to 10mil trace width.

www.ti.com

TPS25751

SLVSH93 – OCTOBER 2023

Submit Document Feedback

Product Folder Links: TPS25751

TPS25751D Scheda tecnica(PDF) 65 Page - Texas Instruments

TPS25751D Scheda tecnica(HTML) 65 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

Scheda tecnica Scarica

Link URL