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DCL540C01 Scheda tecnica(PDF) 29 Page - Toshiba Semiconductor |
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DCL540C01 Scheda tecnica(HTML) 29 Page - Toshiba Semiconductor |
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29 / 31 page ![]() DCL540x01,DCL541x01 29 2023-04-27 Rev.1.3 © 2021-2023 Toshiba Electronic Devices & Storage Corporation 14. Application Note 14-1. Eye diagram The following figure shows typical eye diagrams of DCL541xx01 at the maximum data rate of 150Mbps with pseudorandom bit sequences (PRBS), supply voltage 3.0 V for reference only. Fig.14-1 DCL541A01 Eye diagram at 150Mbps 14-2. PCB layout A ceramic capacitor (0.1 μF) should be connected between pin 1 (VDD1) and pin 2 (GND1) for VDD1 and between pin 16 (VDD2) and pin 15 (GND2) for VDD2, and it should be the layout on the IC as close as possible (less than 10mm). Otherwise, the IC may not operate properly. Fig.14-2 Recommended Printed Circuit Board Layout |
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