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DCL540C01 Scheda tecnica(PDF) 6 Page - Toshiba Semiconductor |
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DCL540C01 Scheda tecnica(HTML) 6 Page - Toshiba Semiconductor |
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6 / 31 page ![]() DCL540x01,DCL541x01 6 2023-04-27 Rev.1.3 © 2021-2023 Toshiba Electronic Devices & Storage Corporation (3) DCL541A01/ DCL541B01 VDD1 VDD2 INPUT DISABLE (DISx) INPUT (VIx) OUTPUT (VOx) COMMENTS PU PU L or OPEN L L Normal Operation H H OPEN Default Default mode DCL541A01=L , DCL541B01=H H X Input Disable mode DCL541A01=L , DCL541B01=H PD X X Undetermined When VDD2 is unpowered, a channel output is undetermined. PD X H X Don't use Don’t use, since a certain voltage will be output through the internal ESD circuit. X H PU L or OPEN L or OPEN Default Default mode DCL541A01=L , DCL541B01=H PD Undetermined When VDD2 is unpowered, a channel output is undetermined. VDDI: Input VDDx , VDDO: Output VDDx , PU= Powered up (VDD≥2.25 V), PD=Powered down (VDD≤1.7 V), H=High Level, L=Low Level, X= Don’t care |
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