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DCL540C01 Scheda tecnica(PDF) 4 Page - Toshiba Semiconductor |
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DCL540C01 Scheda tecnica(HTML) 4 Page - Toshiba Semiconductor |
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4 / 31 page ![]() DCL540x01,DCL541x01 4 2023-04-27 Rev.1.3 © 2021-2023 Toshiba Electronic Devices & Storage Corporation 5.1. Pin Functions PIN I/O DESCRIPTION NAME DCL540 C01 / D01 DCL540 L01 / H01 DCL541 A01 / B01 VDD1 1 1 1 - Power Supply, side 1 GND1 2 2 2 - GND connection for VDD1 , side 1 VI1 3 3 3 I Input, Channel1 VI2 4 4 4 I Input, Channel2 VI3 5 5 5 I Input, Channel3 VI4 6 6 11 I Input, Channel4 NC 7 7 - - Non connected DIS1 - - 7 I Input disable 1. Input pins on side 1 are disabled when DIS1 is high, and in enabled state when DIS1 is low or open. GND1 8 8 8 - GND connection for VDD1, side 1 GND2 9 9 9 - GND connection for VDD2, side 2 DIS2 - - 10 I Input disable 2. Input pins on side 2 are disabled when DIS2 is high, and in enabled state when DIS2 is low or open. EN2 - 10 - I Input enable 2. Input pins on side 2 are enabled when EN2 is high or open, and in high impedance state when EN2 is low. NC 10 - - - Non connected Vo4 11 11 6 O Output, Channel4 Vo3 12 12 12 O Output, Channel3 Vo2 13 13 13 O Output, Channel2 Vo1 14 14 14 O Output, Channel1 GND2 15 15 15 - GND connection for VDD2, side 2 VDD2 16 16 16 - Power Supply, side 2 |
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