DCL540x01,DCL541x01

8

2023-04-27

Rev.1.3

© 2021-2023

Toshiba Electronic Devices & Storage Corporation

9. Electrical Characteristics

9.1. Electrical Characteristics

– ５V Supply

All typical specifications are at Ta=25 °C、VDD1=VDD2=5 V. Minimum/maximum specifications apply over the entire

recommended operating range of 4.5 V≤VDD1≤5.5 V, 4.5 V≤VDD2≤5.5 V, and -40 °C≤Ta≤110 °C, unless otherwise noted.

PARAMETER

TEST CONDITIONS

Fig.

SYMBOL

MIN

TYP.

MAX

UNIT

DC SPECIFICATIONS

Under voltage Lockout

Threshold when supply

voltage is rising

12-1

VDDxUV+

-

2.1

2.25

V

Threshold when supply

voltage is falling

VDDxUV-

1.7

1.9

-

Supply voltage hysteresis

VDDxUVH

0.1

0.2

-

Output Voltage

Logic High

VIx=H , IOH=-20 μA

12-2

VOH

VDDO(1)-0.1

VDDO(1)

-

V

VIx=H , IOH=-4 mA

VDDO(1)-0.4

VDDO(1)-0.2

-

Output Voltage

Logic Low

VIx=L , IOL =20 μA

12-2

VOL

-

0.0

0.1

V

VIx=L , IOL =4 mA

-

0.2

0.4

Output impedance

-

12-2

ZO

-

50

-

Ω

High-level input voltage

-

12-3

VIH

0.7*VDDI(1)

-

-

V

Low-level input voltage

-

12-3

VIL

-

-

0.3*VDDI(1)

V

Input Voltage Hysteresis

-

12-3

VHYS

-

0.37

-

V

Input Current

VI= VDDI(1) or 0 V

-

II

-

-

±10

μA

SWITCHING SPECIFICATIONS

Data Rate

-

-

tbps

DC

-

150

Mbps

Pulse Width

-

-

PW

6.6

-

-

ns

Propagation Delay

50 kHz,Duty=50 %,

tr=tf=2 ns,CL=15 pF

12-4

tPHL , tPLH

-

10.9

18.3

ns

Pulse Width Distortion

|tPHL – tPLH|

12-4

PWD

-

0.8

2.8

ns

Propagation Delay Skew

(Between any two units)

Note (2)

-

tPSK

-

-

10

ns

Channel Matching

Same Direction

12-4

tskCD

-

-

3.2

ns

Opposing Direction

12-4

tskOD

-

-

3.6

Output Rise Time

10 % - 90 %

12-4

tr

-

0.9

-

ns

Output Fall Time

90 % - 10 %

12-4

tf

-

0.9

-

ns

Enable 3-state output

enable time

50 kHz, Duty=50 %,

tr=tf=2 ns,CL=15 pF

Note (3)

12-5

tpZL , tpZH

-

-

15.0

ns

Enable 3-state output

disable time

12-5

tpLZ , tpHZ

-

-

18.0

ns

Disable output enable time

50 kHz, Duty=50 %,

tr=tf=2 ns,CL=15 pF

12-6

tp_EN ,

-

-

23.0

ns

Disable output disable time

12-6

tp_DIS

-

-

23.0

ns

Common mode transient

immunity

VI= VDDI or 0 V,

VCM=1500 V, Ta=25 °C

12-7

CMTI

100

-

-

kV/μs

Note (1) VDDI=Input-side VDDx , VDDO=Output-side VDDx

Note (2) Propagation delay difference (between parts) is applied under the same operating conditions

(power supply voltage. input current, temperature conditions, etc)..

Note (3) When EN2 signal is changed from Low to High or OPEN, the output signal(VOx) is valid after the output enable

time. The output signal(VOx) within the output enable time is undefined.