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DCL540C01 Scheda tecnica(PDF) 14 Page - Toshiba Semiconductor |
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DCL540C01 Scheda tecnica(HTML) 14 Page - Toshiba Semiconductor |
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14 / 31 page ![]() DCL540x01,DCL541x01 14 2023-04-27 Rev.1.3 © 2021-2023 Toshiba Electronic Devices & Storage Corporation 10.Insulation Specifications PARAMETER Symbol TEST CONDITIONS VALUE UNIT Minimum External Clrearance CLR - 8 mm Minimum External Creepage CPG - 8 mm Distance Through The Insulation DTI - 17 μm Comparative Tracking Index CTI - 400 V Material Group - According to IEC 60664-1 II - Overvoltage Category Per IEC 60664-1 - Related Mains Voltage ≤ 300 VRMS I-IV - - Related Mains Voltage ≤ 600 VRMS I-IV - - Related Mains Voltage ≤ 1000 VRMS I-III - DIN VDE V 0884-11(VDE V 0884-11) Maximum Repititive Peak Isolation Voltage VIORM AC voltage (bipolar) 1414 VPK Maximum Transient Isolation Voltage VIOTM VTEST = VIOTM, t = 60 s (qualification) , VTEST= VIOTM, t = 1 s (100 % production) 8000 VPK Maximum surge isolation voltage VIOSM Test method per IEC 60065, 1.2/50 μs waveform, VTEST = 1.6 × VIOSM (qualification) 8000 VPK Apparent charge measuring voltage Vpd(m) Method A, After Input/Output safety test subgroup2&3, VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC 1697 VPK Method A, After environmental tests subgroup 1, VIORM × 1.6 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC 2263 Method B2; At routine test (100 % production) and preconditioning (type test) VIORM × 1.875 = Vpd (m), 100 % production test, tini = tm = 1 sec, partial discharge < 5 pC 2652 Barrier capacitance, input to output CIO f = 1MHz 1.5 pF Input Capacitance CI VIx 1.8 pF Isolation Resistance RIO VIO = 500 V, TA = 25 °C >1012 Ω VIO = 500 V, 100 °C ≤ TA ≤ 110 °C >1011 VIO = 500 V at TS = 150 °C >109 Pollution Degree - - 2 - Climaic Category - - 40/110/21 - UL 1577 Maximum Withstanding Isolation Voltage VISO VTEST = VISO , t = 60 s (qualification), VTEST = 1.2 × VISO , t = 1 s (100 % production) 5000 VRMS |
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