DSPIC30F2012AT20ESLASHML datasheet(87/205 Pages) MICROCHIP

87 / 205 page

DS70139E-page 85

dsPIC30F2011/2012/3012/3013

12.0

OUTPUT COMPARE MODULE

This section describes the output compare module and

associated operational modes. The features provided

by this module are useful in applications requiring oper-

ational modes, such as:

• Generation of Variable Width Output Pulses

• Power Factor Correction

Figure 12-1 depicts a block diagram of the output

compare module.

The key operational features of the output compare

module include:

• Timer2 and Timer3 Selection mode

• Simple Output Compare Match mode

• Dual Output Compare Match mode

• Simple PWM mode

• Output Compare During Sleep and Idle modes

• Interrupt on Output Compare/PWM Event

These operating modes are determined by setting the

appropriate bits in the 16-bit OC1CON and OC2CON

registers. The dsPIC30F2011/2012/3012/3013 devices

have 2 compare channels.

OCxRS and OCxR in Figure 12-1 represent the Dual

Compare registers. In the Dual Compare mode, the

OCxR register is used for the first compare and OCxRS

is used for the second compare.

FIGURE 12-1:

OUTPUT COMPARE MODE BLOCK DIAGRAM

Note: This data sheet summarizes features of this group

of dsPIC30F devices and is not intended to be a complete

reference source. For more information on the CPU,

peripherals, register descriptions and general device

functionality, refer to the “dsPIC30F Family Reference

Manual” (DS70046).

OCxR

Comparator

Output

Logic

OCM<2:0>

Output

OCx

Set Flag bit

OCxIF

OCxRS

Mode Select

Note:

Where ‘x’ is shown, reference is made to the registers associated with the respective output compare

channel (1 or 2).

OCFA

OCTSEL

T2P2_MATCH

TMR2<15:0

TMR3<15:0>

T3P3_MATCH

From GP

(for x = 1, 2, 3 or 4)

Timer Module

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