DSPIC30F2012AT20ESLASHML datasheet(89/205 Pages) MICROCHIP

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DS70139E-page 87

dsPIC30F2011/2012/3012/3013

12.4.2

PWM PERIOD

The PWM period is specified by writing to the PRx

Equation 12-1.

EQUATION 12-1:

PWM frequency is defined as 1/[PWM period].

When the selected TMRx is equal to its respective

period register, PRx, the following four events occur on

the next increment cycle:

• TMRx is cleared.

• The OCx pin is set.

- Exception 1: If PWM duty cycle is 0x0000,

the OCx pin remains low.

- Exception 2: If duty cycle is greater than PRx,

the pin remains high.

• The PWM duty cycle is latched from OCxRS into

OCxR.

• The corresponding timer interrupt flag is set.

See Figure 12-2 for key PWM period comparisons.

Timer3 is referred to in Figure 12-2 for clarity.

FIGURE 12-2:

PWM OUTPUT TIMING

12.5

Output Compare Operation During

CPU Sleep Mode

When the CPU enters Sleep mode, all internal clocks

are stopped. Therefore, when the CPU enters the

Sleep state, the output compare channel drives the pin

to the active state that was observed prior to entering

the CPU Sleep state.

For example, if the pin was high when the CPU entered

the Sleep state, the pin remains high. Likewise, if the

pin was low when the CPU entered the Sleep state, the

pin remains low. In either case, the output compare

module resumes operation when the device wakes up.

12.6

Output Compare Operation During

CPU Idle Mode

When the CPU enters the Idle mode, the output

compare module can operate with full functionality.

The output compare channel operates during the CPU

Idle mode if the OCSIDL bit (OCxCON<13>) is at logic

‘0’ and the selected time base (Timer2 or Timer3) is

enabled and the TSIDL bit of the selected timer is set

to logic ‘0’.

12.7

Output Compare Interrupts

The output compare channels have the ability to gener-

ate an interrupt on a compare match, for whichever

Match mode has been selected.

For all modes except the PWM mode, when a compare

event occurs, the respective interrupt flag (OCxIF) is

asserted and an interrupt is generated if enabled. The

OCxIF bit is located in the corresponding IFS register

and must be cleared in software. The interrupt is

enabled via the respective compare interrupt enable

(OCxIE) bit located in the corresponding IEC Control

For the PWM mode, when an event occurs, the respec-

tive timer interrupt flag (T2IF or T3IF) is asserted and

an interrupt is generated if enabled. The IF bit is

located in the IFS0 register and must be cleared in soft-

ware. The interrupt is enabled via the respective timer

interrupt enable bit (T2IE or T3IE) located in the IEC0

Control register. The output compare interrupt flag is

never set during the PWM mode of operation.

PWM period = [(PRx) + 1] • 4 • TOSC •

(TMRx prescale value)

Period

Duty Cycle

TMR3 = Duty Cycle

TMR3 = PR3

T3IF = 1

(Interrupt Flag)

OCxR = OCxRS

TMR3 = PR3

(Interrupt Flag)

OCxR = OCxRS

T3IF = 1

(OCxR)

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