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STR750FV2 Scheda tecnica(PDF) 58 Page - STMicroelectronics |
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STR750FV2 Scheda tecnica(HTML) 58 Page - STMicroelectronics |
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58 / 81 page ![]() Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx 58/81 NRSTIN and NRSTOUT pins NRSTIN Pin Input Driver is TTL/LVTTL as for all GP I/Os. A permanent pull-up is present which is the same as RPU (see : General characteristics on page 54) NRSTOUT Pin Output Driver is equivalent to the O2 type driver except that it works only as an open-drain (the P-MOS is de-activated). A permanent pull-up is present which is the same as RPU (see : General characteristics on page 54) Subject to general operating conditions for VDD_IO and TA unless otherwise specified. Table 35. NRSTIN and NRSTOUT pins Symbol Parameter Conditions Min Typ 1) Max Unit VIL(NRSTIN) NRSTIN Input low level voltage(1) 1. Data based on product characterisation, not tested in production. 0.8 V VIH(NRSTIN) NRSTIN Input high level voltage(1) 2 Vhys(NRSTIN) NRSTIN Schmitt trigger voltage hysteresis(2) 2. Hysteresis voltage between Schmitt trigger switching levels. 400 mV VOL(NRSTIN) NRSTOUT Output low level voltage(3) 3. The IIO current sunk must always respect the absolute maximum rating specified in Section 5.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. IIO=+2 mA 0.4 V RPU(NRSTIN) NRSTIN Weak pull-up equivalent resistor(4) 4. The RPU pull-up equivalent resistor are based on a resistive transistor VIN=VSS VDD_IO=3.3 V 25 50 100 k Ω VDD_IO=5 V 20 31 100 k Ω tw(RSTL)out Generated reset pulse duration (visible at NRSTOUT pin)(5) 5. To guarantee the reset of the device, a minimum pulse of 15 µs has to be applied to the internal reset. At VDD_IO power-up, the built-in reset stretcher may not generate the 15 µs pulse duration while once VDD_IO is established, an external reset pulse will be internally stretched up to 15 µs thanks to the reset pulse stretcher. Internal reset source 15 20 µs th(RSTL)in External reset pulse hold time at NRSTIN pin(6) 6. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy environments. At VDD_IO power-up (5) 20 µs When VDD_IO is established(5) 1 µs tg(RSTL)in maximum negative spike duration filtered at NRSTIN pin(7) 7. In fact the filter is made to ignore all incoming pulses with short duration: - all negative spikes with a duration less than 150 ns are filtered - all trains of negative spikes with a ratio of 1/2 are filtered. This means that all spikes with a maximum duration of 150 ns with minimum interval between spikes of 75 ns are filtered. Data guaranteed by design, not tested in production. The time between two spikes must be higher than 1/2 of the spike duration. 150 ns |
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