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STR750FV2 Scheda tecnica(PDF) 62 Page - STMicroelectronics

Il numero della parte STR750FV2
Spiegazioni elettronici  ARM7TDMI-S??32-bit MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CAN
PDF  81 Pages
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Produttore elettronici  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STR750FV2 Scheda tecnica(HTML) 62 Page - STMicroelectronics

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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
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5.3.10
Communication interface characteristics
SSP Synchronous Serial Peripheral in Master mode (SPI or TI mode)
General operating conditions: V33, 3.0V to 3.3V, V18 =1.8V, CL
≈ 45 pF.
Table 38.
SSP Master mode characteristics(1)
1.
Data based on characterisation results, not tested in production.
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
SPI clock frequency(2)
2.
Max frequency for the 2 SSPs is fPCLK/2; fPCLK max = 32 MHz. This takes into account the frequency
limitation due to I/O speed capability. SSP0 uses IO4 type while SSP1 uses IO2 type I/Os.
SSP0
16
MHz
SSP1
8
tr(SCK)
SPI clock rise time
SSP0
14
ns
SSP1
33
tf(SCK)
SPI clock fall time
SSP0
11
SSP1
30
tw(SCKH)
tw(SCKL)
SCK high and low time
SSP0
19
SSP1
30
tNSSLQV
NSS low to Data Output
MOSI valid time
SSP0
0.5tSCK+15ns
SSP1
0.5tSCK+30ns
tSCKNSSH
SCK last edge to NSS high
CPHA = 0
SSP0
0.5tSCK+15ns
SSP1
0.5tSCK+30ns
CPHA = 1
SSP0
tSCK+15ns
SSP1
tSCK+30ns
tSCKQV
SCK trigger edge to data
output MOSI valid time
SSP0
15
SSP1
30
tSCKQX
SCK trigger edge to data
output MOSI invalid time
SSP0
0
SSP1
0
tsu
Data input (MISO) setup
time w.r.t SCK sampling
edge
SSP0
25
SSP1
25
th
Data input (MISO) hold time
w.r.t SCK sampling edge
SSP0
0
SSP1
0



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