TSC2007 datasheet(21/43 Pages) TI2

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SDA

SCL

3-8

SlaveAddress

MSB

RepeatedIfMoreBytesAreTransferred

R/W

DirectionBit

Acknowledgement

SignalfromReceiver

Acknowledgement

SignalfromReceiver

START

Condition

ACK

STOPCondition

orRepeated

STARTCondition

TSC2007-Q1

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SBAS545A – SEPTEMBER 2011 – REVISED DECEMBER 2016

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Programming (continued)

The TSC2007-Q1 may operate in the following two modes:

1. Slave Receiver Mode: Serial data and clock are received through SDA and SCL. After each byte is

received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning

and end of a serial transfer. Address recognition is performed by hardware after reception of the slave

address and direction bit.

2. Slave Transmitter Mode: The first byte (the slave address) is received and handled as in the slave receiver

mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data are

transmitted on SDA by the TSC2007-Q1 while the serial clock is input on SCL. START and STOP conditions

are recognized as the beginning and end of a serial transfer.

7.5.1.1 I2C Fast or Standard Mode (F/S Mode)

In I2C Fast or Standard (F/S) mode, serial data transfer must meet the timing shown in the Specifications section.

In the serial transfer format of F/S mode, the master signals the beginning of a transmission to a slave with a

START condition (S), which is a high-to-low transition on the SDA input while SCL is high. When the master has

finished communicating with the slave, the master issues a STOP condition (P), which is a low-to-high transition

on SDA while SCL is high, as shown in Figure 28. The bus is free for another transmission after a STOP

condition has occurred. Figure 28 shows the complete F/S mode transfer on the I2C, 2-wire serial interface. The

address byte, control byte, and data byte are transmitted between the START and STOP conditions. The SDA

state is only allowed to change while SCL is low, except for the START and STOP conditions. Data are

transmitted in 8-bit words. Nine clock cycles are required to transfer the data into or out of the device (8-bit word

plus acknowledge bit).

Figure 28. Complete Fast-Mode or Standard-Mode Transfer

7.5.1.2 I2C High-Speed Mode (HS Mode)

The TSC2007-Q1 can operate with high-speed I2C masters. To do so, the pullup resistor on SCL must be

changed to an active pullup, as recommended in the I2C specification.

Serial data transfer format in High-Speed (HS) mode meets the Fast or Standard (F/S) mode I2C bus

specification. HS mode can only commence after the following conditions (all of which are in F/S mode) exist:

1. START condition (S)

2. 8-bit master code (00001xxx)

3. Not-acknowledge bit (N)

Figure 29 shows this sequence in more detail. HS-mode master codes are reserved 8-bit codes used only for

triggering HS mode, and are not to be used for slave addressing or any other purpose. The master code

indicates to other devices that an HS-mode transfer is about to begin and the connected devices must meet the

HS-mode specification. Because no device is allowed to acknowledge the master code, the master code is

followed by a not-acknowledge bit (N).

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