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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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TSC2007 Scheda tecnica(PDF) 6 Page - Texas Instruments |
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TSC2007 Scheda tecnica(HTML) 6 Page - Texas Instruments |
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6 / 43 page  6 TSC2007-Q1 SBAS545A – SEPTEMBER 2011 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: TSC2007-Q1 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Electrical Characteristics (continued) TA = –40°C to 85°C, VDD = 1.2 V to 3.6 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT AND OUTPUT Logic family CMOS Logic level VIH 1.2 V ≤ VDD < 1.6 V 0.7 × VDD VDD + 0.3 V 1.6 V ≤ VDD ≤ 3.6 V 0.7 × VDD VDD + 0.3 V VIL 1.2 V ≤ VDD < 1.6 V –0.3 0.2 × VDD V 1.6 V ≤ VDD ≤ 3.6 V –0.3 0.3 × VDD V IIL SCL and SDA pins –1 1 µA CIN (2) SCL and SDA pins 10 pF VOH IOH = 2 TTL loads VDD – 0.2 VDD V VOL IOL = 2 TTL loads 0 0.2 V ILEAK Floating output –1 1 µA COUT (2) Floating output 10 pF Data format Straight binary POWER-SUPPLY REQUIREMENTS Quiescent supply current (VDD with sensor off) 12-bit Fast mode (clock = 400 kHz) PD[1:0] = 0,0 VDD = 1.2 V, 32.56k eq rate 128 190 µA VDD = 1.2 V, 8.2k eq rate 32.24 µA VDD = 1.8 V, 34.42k eq rate 165 240 µA VDD = 1.8 V, 8.2k eq rate 39.31 µA VDD = 2.7 V, 34.79k eq rate 226.2 335 µA VDD = 2.7 V, 8.2k eq rate 53.32 µA Power down supply current Not addressed, SCL = SDA = 1 0 0.8 µA POWER-ON AND OFF SLOPE REQUIREMENTS (2) VDD off ramp TA = –40°C to 85°C 2 kV/s VDD off time TA = –40°C to 85°C, VDD = 0 V 1.2 s TA = –20°C to 85°C, VDD = 0 V 0.3 s VDD on ramp TA = –40°C to 85°C 12 kV/s 6.6 Timing Requirements: Standard Mode (SCL = 100 kHz) TA = –40°C to 85°C, VDD = 1.6 V (unless otherwise noted). MIN NOM MAX UNIT fSCL SCL clock frequency 0 100 kHz tBUF Bus free time between a STOP and START condition 4.7 µs tHD, STA Hold time (repeated) START condition 4 µs tLOW Low period of SCL clock 4.7 µs tHIGH High period of the SCL clock 4 µs tSU, STA Setup time for a repeated START condition 4.7 µs tHD, DAT Data hold time 0 3.45 µs tSU, DAT Data setup time 250 ns tR Rise time for both SDA and SCL signals (receiving) Cb = total bus capacitance 1000 ns tF Fall time for both SDA and SCL signals Receiving Cb = total bus capacitance 300 ns Transmitting Cb = total bus capacitance 250 ns tSU, STO Setup time for STOP condition 4 µs Cb Capacitive load for each bus line Cb = total capacitance of one bus line in pF 400 pF Cycle time 8 bits 40 SCL + 127 CCLK, VDD = 1.8 V 434.7 µs 12 bits 49 SCL + 148 CCLK, VDD = 1.8 V 570.9 µs Effective throughput 8 bits VDD = 1.8 V 2.3 kSPS 12 bits VDD = 1.8 V 1.75 kSPS Equivalent rate = effective throughput × 7 8 bits VDD = 1.8 V 16.1 kHz 12 bits VDD = 1.8 V 12.26 kHz |
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