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TSC2007-Q1

SBAS545A – SEPTEMBER 2011 – REVISED DECEMBER 2016

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Copyright © 2011–2016, Texas Instruments Incorporated

(1)

The setup command has an additional four bits of data. These data are static; that is, they are not changed by other commands, except

for the power-on reset. The default value for these bits after power-on reset is 0000. Table 5 shows the definition of these data bits.

Table 4. Converter Function Select

C3

C2

C1

C0

FUNCTION

INPUT TO A-D

CONVERTER

X-DRIVERS Y-DRIVERS

ACK

REFERENCE

MODE

0

0

0

0

Measure TEMP0

TEMP0

OFF

OFF

Y

Single-Ended

0

0

0

1

Reserved

—

OFF

OFF

N

Single-Ended

0

0

1

0

Measure AUX

AUX

OFF

OFF

Y

Single-Ended

0

0

1

1

Reserved

—

OFF

OFF

N

Single-Ended

0

1

0

0

Measure TEMP1

TEMP1

OFF

OFF

Y

Single-Ended

0

1

0

1

Reserved

—

OFF

OFF

N

Single-Ended

0

1

1

0

Reserved

—

OFF

OFF

N

Single-Ended

0

1

1

1

Reserved

—

OFF

OFF

N

Single-Ended

1

0

0

0

Activate X-drivers

—

ON

OFF

Y

Differential

1

0

0

1

Activate Y-drivers

—

OFF

ON

Y

Differential

1

0

1

0

Activate Y+, X-drivers

—

X– ON

Y+ ON

Y

Differential

1

0

1

1

Setup command(1)

—

OFF

OFF

N

—

1

1

0

0

Measure X position

Y+

ON

OFF

Y

Differential

1

1

0

1

Measure Y position

X+

OFF

ON

Y

Differential

1

1

1

0

Measure Z1 position

X+

X– ON

Y+ ON

Y

Differential

1

1

1

1

Measure Z2 position

Y–

X– ON

Y+ ON

Y

Differential

Table 5. Command Byte Definition for the Setup Command

BIT

NAME

DESCRIPTION

D7–D4

C3–C0

Setup command; must write 1011.

D3–D2

PD1–PD0

Reserved; must write 00.

D1

Filter control

0: Use the onboard MAV filter (default).

1: Bypass the onboard MAV filter.

D0

RIRQ select

PENIRQ pullup resistor (RIRQ) select

0: RIRQ = 50 kΩ (default).

1: RIRQ = 90 kΩ.

7.5.2.3 Start a Converter Function or Write Cycle

A conversion or write cycle begins when the master issues the address byte containing the slave address of the

TSC2007-Q1, with the eighth bit equal to a 0 (R/W = 0), as shown in Table 2. Once the eighth bit has been

received, and the address matches the A1–A0 address input pin setting, the TSC2007-Q1 issues an

acknowledge.

When the master receives the acknowledge bit from the TSC2007-Q1, the master writes the command byte to

the slave (see Table 3). After the command byte is received by the slave, the slave issues another acknowledge

bit. The master then ends the write cycle by issuing a repeated START or a STOP condition, as shown in

Figure 30.