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TSC2007 Scheda tecnica(PDF) 7 Page - Texas Instruments |
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TSC2007 Scheda tecnica(HTML) 7 Page - Texas Instruments |
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7 / 43 page  7 TSC2007-Q1 www.ti.com SBAS545A – SEPTEMBER 2011 – REVISED DECEMBER 2016 Product Folder Links: TSC2007-Q1 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated 6.7 Timing Requirements: Fast Mode (SCL = 400 kHz) All specifications typical at –40°C to 85°C, VDD = 1.6 V (unless otherwise noted). MIN NOM MAX UNIT fSCL SCL clock frequency 0 400 kHz tBUF Bus free time between a STOP and START condition 1.3 µs tHD, STA Hold time (repeated) START condition 0.6 µs tLOW Low period of SCL clock 1.3 µs tHIGH High period of the SCL clock 0.6 µs tSU, STA Setup time for a repeated START condition 0.6 µs tHD, DAT Data hold time 0 0.9 µs tSU, DAT Data setup time 100 ns tR Rise time for both SDA and SCL signals (receiving) Cb = total bus capacitance 20 + 0.1 × Cb 300 ns tF Fall time for both SDA and SCL signals Receiving Cb = total bus capacitance 20 + 0.1 × Cb 300 ns Transmitting Cb = total bus capacitance 20 + 0.1 × Cb 250 ns tSU, STO Setup time for STOP condition 0.6 µs Cb Capacitive load for each bus line Cb = total capacitance of one bus line in pF 400 pF Cycle time 8 bits 40 SCL + 127 CCLK, VDD = 1.8 V 134.7 µs 12 bits 49 SCL + 148 CCLK, VDD = 1.8 V 203.4 µs Effective throughput 8 bits VDD = 1.8 V 7.42 kSPS 12 bits VDD = 1.8 V 4.92 kSPS Equivalent rate = effective throughput × 7 8 bits VDD = 1.8 V 51.97 kHz 12 bits VDD = 1.8 V 34.42 kHz 6.8 Timing Requirements: High-Speed Mode (SCL = 1.7 MHz) All specifications typical at –40°C to 85°C, VDD = 1.6 V (unless otherwise noted). MIN NOM MAX UNIT fSCL SCL clock frequency 0 1.7 MHz tHD, STA Hold time (repeated) START condition 160 ns tLOW Low period of SCL clock 320 ns tHIGH High period of the SCL clock 120 ns tSU, STA Setup time for a repeated START condition 160 ns tHD, DAT Data hold time 0 150 ns tSU, DAT Data setup time 10 ns tR Rise time for a signal (receiving) SCL Cb = total bus capacitance 20 80 ns SDA Cb = total bus capacitance 20 160 ns tF Fall time for a signal (receiving) SCL Cb = total bus capacitance 20 80 ns SDA Cb = total bus capacitance 20 160 ns tF Fall time for both SDA and SCL signals (transmitting) Cb = total bus capacitance 20 160 ns tSU, STO Setup time for STOP condition 160 ns Cb Capacitive load for each bus line Cb = total capacitance of one bus line in pF 400 pF Cycle time 8 bits 40 SCL + 127 CCLK, VDD = 1.8 V 58.2 µs 12 bits 49 SCL + 148 CCLK, VDD = 1.8 V 109.7 µs Effective throughput 8 bits VDD = 1.8 V 17.17 kSPS 12 bits VDD = 1.8 V 9.12 kSPS Equivalent rate = effective throughput × 7 8 bits VDD = 1.8 V 120.22 kHz 12 bits VDD = 1.8 V 63.81 kHz |
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