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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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TSC2007 Scheda tecnica(PDF) 8 Page - Texas Instruments |
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TSC2007 Scheda tecnica(HTML) 8 Page - Texas Instruments |
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8 / 43 page  t HD, STA t SU, DAT t HD, DAT t SU, STA t SU, STO t HD, STA t LOW t HIGH t R t F t BUF SDA START CONDITION START CONDITION STOP CONDITION REPEATED START CONDITION SCL 8 TSC2007-Q1 SBAS545A – SEPTEMBER 2011 – REVISED DECEMBER 2016 www.ti.com Product Folder Links: TSC2007-Q1 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated 6.9 Timing Requirements: High-Speed Mode (SCL = 3.4 MHz) All specifications typical at –40°C to 85°C, VDD = 1.6 V (unless otherwise noted). MIN NOM MAX UNIT fSCL SCL clock frequency 0 3.4 MHz tHD, STA Hold time (repeated) START condition 160 ns tLOW Low period of SCL clock 160 ns tHIGH High period of the SCL clock 60 ns tSU, STA Setup time for a repeated START condition 160 ns tHD, DAT Data hold time 0 70 ns tSU, DAT Data setup time 10 ns tR Rise time for a signal (receiving) SCL Cb = total bus capacitance 10 40 ns SDA Cb = total bus capacitance 10 80 ns tF Fall time for a signal (receiving) SCL Cb = total bus capacitance 10 40 ns SDA Cb = total bus capacitance 10 80 ns tF Fall time for both SDA and SCL signals (transmitting) Cb = total bus capacitance 10 80 ns tSU, STO Setup time for STOP condition 160 ns Cb Capacitive load for each bus line Cb = total capacitance of one bus line in pF 100 pF Cycle time 8 bits 40 SCL + 127 CCLK, VDD = 1.8 V 46.5 µs 12 bits 49 SCL + 148 CCLK, VDD = 1.8 V 95.3 µs Effective throughput 8 bits VDD = 1.8 V 21.52 kSPS 12 bits VDD = 1.8 V 10.49 kSPS Equivalent rate = effective throughput × 7 8 bits VDD = 1.8 V 150.65 kHz 12 bits VDD = 1.8 V 73.46 kHz Figure 1. Detailed I/O Timing |
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