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PL460 Scheda tecnica(PDF) 35 Page - Microchip Technology |
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PL460 Scheda tecnica(HTML) 35 Page - Microchip Technology |
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35 / 48 page ![]() PL460 Electrical Characteristics Data Sheet © 2020-2023 Microchip Technology Inc. and its subsidiaries DS60001666D - 35 Table 11-4. TFBGA81 Electrical Pinout (continued) Pin No. Pin Name I/O I(mA) Res. HY Pin No. Pin Name I/O I(mA) Res. HY B9 PGND P — — — G5 GND — — — — C1 VDDCORE P — — — G6 VDDIO P — — — C2 VDDCORE P — — — G7 G1 I/O ±2/4 PU/PD/- Y/- C3 GND P — — — G8 CS I/O ± 2/4 PU/PD/- Y/- C4 GND P — — — G9 MOSI I/O ± 2/4 PU/PD/- Y/- C5 GND P — — — H1 VDDIN_AN P — — — C6 GNDAMP P — — — H2 STBY I — — Y C7 VDDAMP P — — — H3 XIN I — — — C8 PGND P — — — H4 GND P — — — C9 ASO0 O 1200 (3) — — H5 VDDCORE P — — — D1 VDDIO P — — — H6 VDDIN P — — — D2 VDDIO P — — — H7 THEN I/O ±2/4 PU/PD/- Y/- D3 VDDIO P — — — H8 EXTIN I/O ± 2/4 PU/PD/- Y/- D4 GND P — — — H9 SCK I/O ± 2/4 PU/PD/- Y/- D5 GND P — — — J1 GND P — — — D6 NC — — — — J2 VZC I — (5) Y D7 GND P — — — J3 XOUT O — — — D8 VDDAMP P — — — J4 VDDPLL P — — — D9 ASO0 O 1200 (3) — — J5 VDDCORE P — — — E1 VIN I — — — J6 VDDIN — — — — E2 AGND P — — — J7 ENABLE I — — Y E3 GND P — — — J8 TXEN I/O ±2/4 PU/PD/- Y/- E4 VDDIO P — — — J9 GND P — — — E5 NC — — — — — — — — — — I/O = Pin Direction (I = Input, O = Output, T = Tri-state, P = Power) I(mA) = Nominal Current (+ = source, - = sink) Res = Pin pull-up/pull-down resistor (PU = Pull Up, PD = Pull Down (70-140 kΩ, typical 100 kΩ)) HY = Input Hysteresis (Y = yes) Notes: 1. Maximum value considering the use of both balls per EMITx. 2. Maximum value considering the use of both balls of OUT. 3. Maximum value considering the use of both balls per ASOx. 4. Selectable from 5 mA to 20 mA in 4 steps of 5 mA. 5. In case of fuse programming, an external 10 kΩ serial resistor is needed (see Fuse Programming). 6. VREGP, VREGN, VREFP, VREFC, and VREFN are analog signals. |
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