PL460 datasheet(8/48 Pages) MICROCHIP

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PL460

Signal Description

Data Sheet

DS60001666D - 8

Table 3-1. Signal Description List (continued)

Signal Name

Function

Type

Active

Level

Voltage

Reference

Comments

EMIT[2:3]

PLC Tri-state Transmission ports

Output

—

VDDIO

—

TXRX1

Analog Front-End Transmission/Reception

for the auxiliary transmission branch.

This

digital

output

used

modify external coupling behavior in

Transmission/Reception

Output

—

VDDIO

—

Input/Output

STBY

Enable Sleep mode of the modem

Input

High

VDDIO

(Note 16)

EXTIN

Indication of pending events

Output

Low

VDDIO

—

TXEN

Transmission enabled

Input

High

VDDIO

—

Thermal Monitor

THEN

Enable Thermal Monitor functionality

Input

High

VDDIO

—

NTHW0

Indication of the first thermal warning

Output

—

VDDIO

—

THW1

Indication of the second thermal warning

Output

—

VDDIO

—

General Purpose Input

Input

High

VDDIO

—

Serial Peripheral Interface - SPI

SPI Chip Select

Input

Low

VDDIO

Internal pull up (Note 17)

SCK

SPI Clock signal

Input

—

VDDIO

Internal pull up (Note 17)

MOSI

SPI Host Out Client In

Input

—

VDDIO

Internal pull up (Note 17)

MISO

SPI Host In Client Out

Output

—

VDDIO

—

Notes:

1. Connecting two 100 nF decoupling multilayer ceramic capacitors (MLCC) to the VDDIO and

VDDIN pins is recommended. In addition, for correct PLC transmission using the auxiliary

branch, placing one 4.7 μF decoupling multilayer ceramic capacitor (MLCC) as close as possible

to VDDIO pins, D1 and D3, is strongly recommended.

2. Placing a 100 nF decoupling multilayer ceramic capacitor (MLCC) in the VDDIN_AN pins is

recommended.

3. Placing 100 nF plus 2.2 μF decoupling multilayer ceramic capacitors (MLCC) in each pair of

VDDCORE pins (H5-J5 and C1-C2) is recommended.

4. Placing 100 nF plus 4.7 μF decoupling multilayer ceramic capacitors (MLCC) in the VDDPLL pin is

recommended.

5. A 100 nF multilayer ceramic capacitor (MLCC) is required between the VREGP and PVDDAMP

pads for decoupling and stabilization purposes.

6. A 100 nF multilayer ceramic capacitor (MLCC) is required between the VREGN and GNDAMP pads

for decoupling and stabilization purposes.

7. Placing one 100 uF aluminum Low-ESR 25V capacitor and three 100 nF 25V multilayer ceramic

capacitors (MLCC) in the PVDDAMP pins is recommended.

8. The PLC-protocol firmwares provided by Microchip are configured by default for a power supply

of the PLC driver amplifier of 12V.

9. Placing a 100 nF decoupling multilayer ceramic capacitor (MLCC) in the VDDAMP pins is

recommended.

10. Separate pins are provided for GND, AGND, PGND, and GNDAMP grounds. Taking these layout

considerations into account to reduce interference is recommended. It is recommended to

connect ground pins as short as possible to the system ground plane. For more details about

EMC Considerations, refer to AVR040 Application Note.

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