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PL460

Power Considerations

Data Sheet

DS60001666D - 14

Power Considerations

5.1.

Power Supplies

The following table defines the power supply requirements of the PL460.

Table 5-1. Power Supplies

Name

Associated

Ground

Description

VDDCORE

GND

Core power supply with internal connection to 1.25V voltage regulator output.

VDDIO

GND

3.3V digital supply.

VDDIN

GND

3.3V input for core voltage regulator.

VDDIN_AN

AGND

3.3V analog supply (ADC + PGA).

VDDPLL

GND

1.25V voltage regulator output. To be connected to VDDCORE through a low-pass filter.

PVDDAMP

PGND

8-16V power supply of the embedded PLC driver.

VDDAMP

GNDAMP

3.3V digital and analog supply of PLC driver.

The PL460 embeds a voltage regulator to supply the core. The Voltage Regulator state is controlled

by the ENABLE pin. The VDDCORE pins in the package must be populated with external decoupling

capacitors; connecting one 100 nF and one 2.2 µF capacitor to each pair of VDDCORE pins, C1-C2

and H5-J5, is recommended.

All ground pads GND, AGND, and PGND must be connected at the PCB level. Additionally, it is

recommended to keep PGND and AGND nets in the PCB layout in separate power planes with a

single point connection to GND. Refer to reference designs provided by Microchip for a reference

layout.

Assuming the previously described connections are done, and the following decoupling capacitors

are mandatory at the PCB level:

• MLCC 100 nF 10% 25V X7R 0603 between VREGN and GNDAMP

• MLCC 100 nF 10% 25V X7R 0603 between VREGP and VDD

• MLCC 100 nF 10% 25V X7R 0603 between VDDAMP and GND

PVDDAMP decoupling capacitive network is highly dependent on final application. Refer to the

Signal Description for the recommended decoupling network for NB-PLC cases.

5.2.

Power Constraints

The following power constraints apply to the PL460 device. Deviating from these constraints may

lead to unwanted device behavior.

• PVDDAMP must be stable when transmitting. A variation of 1V above or 2V below the

configured PVDDAMP voltage can damage internal regulators and must be avoided. Microchip

strongly recommends monitoring the PVDDAMP voltage, and if these conditions are detected,

transmissions should be disabled using the TXEN pin.

• VDDIN and VDDIO must have the same level, 3.3V.

• VDDPLL voltage must be derived from VDDCORE through a low-pass filter. Using a second order

LC with a cutoff frequency equal to 25 kHz is recommended. The inductor can be replaced by

a ferrite bead, then a cutoff frequency equal to 75 kHz could be acceptable. In those cases,

it is mandatory to check the communication performances of the system to detect problems

originating from poor PLL supply filtering.

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