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2.3.8

SCI Timing

Table 2.24

SCI timing (1)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol Min

Max Unit Test conditions

SCI Input clock cycle

Asynchronous

tScyc

—

tPcyc Figure 2.25

Clock synchronous

—

Input clock pulse width

tSCKW

0.4

0.6

tScyc

Input clock rise time

tSCKr

—

Input clock fall time

tSCKf

—

Output clock cycle

Asynchronous

tScyc

6 (other than SCI1,

SCI2)

8 (SCI1, SCI2)

—

tPcyc

Clock synchronous

—

Output clock pulse width

tSCKW

0.4

0.6

tScyc

Output clock rise time

tSCKr

—

Output clock fall time

tSCKf

—

Transmit data delay

Clock synchronous master mode (internal

clock)

tTXD

—

Figure 2.26

Clock synchronous slave mode (external

clock)

tTXD

—

Receive data setup time Clock synchronous master mode (internal

clock)

tRXS

—

Clock synchronous slave mode (external

clock)

tRXS

—

Receive data hold time

Clock synchronous

tRXH

—

Note:

tPcyc: PCLKA cycle.

tSCKW

tSCKr

tSCKf

tScyc

SCKn

Note:

n = 0, 3, 4, 9

Figure 2.25

SCK clock input/output timing

RA4E1 Datasheet

2. Electrical Characteristics

R01DS0391EJ0130 Rev.1.30

Jun 6, 2025

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