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Table 2.7

Operating and standby current (2 of 2)

Parameter

Symbol

Min Typ

Max

Unit

Test

conditions

Reference

power

supply

current

(VREFH0)

During 12-bit A/D conversion

AIREFH0

—

120

µA

—

Waiting for 12-bit A/D conversion

—

0.07

0.5

µA

—

ADC12 in standby modes

—

0.07

0.5

µA

—

Reference

power

supply

current

(VREFH)

During D/A conversion

Without AMP output AIREFH

—

0.1

0.4

—

With AMP output

—

0.1

0.4

—

Waiting for D/A conversion

—

0.07

0.8

µA

—

USB

operating

current

Low speed

USB

ICCUSBLS

—

3.5

6.5

VCC_USB

Full speed

USB

ICCUSBFS

—

4.0

10.0

VCC_USB

LDOn operating current (per unit)*15

ICCLDO

—

0.18

—

PLL2-LDO operating current

ICCPLL2LDO —

0.21

—

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Measured with clocks supplied to the peripheral functions. This does not include the BGO operation.

Note 3. ICC depends on f (ICLK) as follows.

ICC Max. = 0.53 × f + 12 (max. operation in high-speed mode)

ICC Typ. = 0.05 × f + 1.85 (normal operation in high-speed mode, all peripheral clocks disabled)

ICC Typ. = 0.12 × f + 0.69 (low-speed mode)

ICC Max. = 0.13 × f + 12 (sleep mode)

Note 4. This does not include the BGO operation.

Note 5. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

Note 6. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (1.563 MHz).

Note 7. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (3.125 MHz).

Note 8. Reference value

Note 9. When the MCU is in Software Standby mode or the MSTPCRD.MSTPD16 (12-Bit A/D Converter 0 Module Stop bit) and

MSTPCRD.MSTPD20 (12-bit D/A converter module stop bit) are in the module-stop state.

Note 10. FCLK, PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (15.6 kHz).

Note 11. PCLKA, PCLKB, PCLKC, and PCLKD are set to divided by 64 (512 Hz). FCLK is the same frequency as that of ICLK.

Note 12. PLL output frequency = 100MHz.

Note 13. PLL output frequency = 200MHz.

Note 14. PLL2-LDO disabled.

Note 15. n = 0, 1

Table 2.8

Coremark and normal mode current

Parameter

Symbol

Typ

Unit

Test conditions

Supply Current*1

Coremark*2 *3 *4

ICC

µA/MHz

ICLK = 100 MHz

PCLKA

= PCLKB

= PCLKC

= PCLKD

= FCLK

= 1.56 MHz

Normal mode

All peripheral

clocks disabled,

cache on,

while (1) code

executing from

flash*2 *3 *4

All peripheral

clocks disabled,

cache off,

while (1) code

executing from

flash*2 *3 *4

118

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

Note 3. PLL output frequency = 100MHz.

Note 4. PLL2-LDO disabled.

RA4E1 Datasheet

2. Electrical Characteristics

R01DS0391EJ0130 Rev.1.30

Jun 6, 2025

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