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SSLn0

input

RSPCKn

CPOL = 0

input

RSPCKn

CPOL = 1

input

MISOn

output

MOSIn

input

tDr, tDf

tSA

tOH

tLEAD

tTD

tLAG

LSB OUT

(Last data)

DATA

MSB OUT

MSB IN

DATA

LSB IN

MSB IN

LSB OUT

tSU

tOD

tREL

MSB OUT

Note:

n = A

Figure 2.39

SPI timing for slave when CPHA = 1

2.3.10

QSPI Timing

Table 2.28

QSPI timing

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit

Test conditions

QSPI

QSPCK clock cycle

tQScyc

tPcyc

Figure 2.40

QSPCK clock high pulse

width

tQSWH

tQScyc × 0.4

—

QSPCK clock low pulse

width

tQSWL

tQScyc × 0.4

—

Data input setup time

tSu

—

Figure 2.41

Data input hold time

tIH

—

QSSL setup time

tLEAD

(N + 0.5) × tQscyc - 5*1

(N + 0.5) × tQscyc +

100*1

QSSL hold time

tLAG

(N + 0.5) × tQscyc - 5*2

(N + 0.5) × tQscyc +

100*2

Data output delay

tOD

—

Data output hold time

tOH

–3.3

—

Successive transmission

delay

tTD

tQScyc

Note:

tPcyc: PCLKA cycle.

Note 1. N is set to 0 or 1 in SFMSLD.

Note 2. N is set to 0 or 1 in SFMSHD.

RA4E1 Datasheet

2. Electrical Characteristics

R01DS0391EJ0130 Rev.1.30

Jun 6, 2025

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