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RZ/T2M Scheda tecnica(PDF) 58 Page - Renesas Technology Corp |
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RZ/T2M Scheda tecnica(HTML) 58 Page - Renesas Technology Corp |
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58 / 128 page  tMDH RES# MD[2:0], MDV[4:0], MDD, MDW Valid Data 2.1 V Figure 2.10 Mode input timing 2.5.3 Bus Timing Table 2.21 Bus timing (1 of 2) Conditions: VOH = VCC33 × 0.5, VOL = VCC33 × 0.5, C = 15 pF (CKIO), 30 pF (others), Tjmin = −40°C Parameter Symbol CKIO = 1/tCKcyc*1 (Max 66 MHz) Unit Reference Figure Min. Max. Address delay time 1 SDRAM*2 tAD1 2 11 ns Figure 2.11 to Figure 2.35 Other than the above 0 10 ns Address delay time 2 tAD2 1/2tCKcyc 1/2tCKcyc + 10 ns Figure 2.18 Address setup time tAS 0 — ns Figure 2.11 to Figure 2.14, Figure 2.18 Chip enable setup time tCS 0 — ns Figure 2.11 to Figure 2.14, Figure 2.18 Address hold time tAH 0 — ns Figure 2.11 to Figure 2.14 BS delay time tBSD — 11 ns Figure 2.11 to Figure 2.32 CSn# delay time 1 SDRAM*2 tCSD1 2 11 ns Figure 2.11 to Figure 2.35 Other than the above 0 10 ns Read/write delay time 1 SDRAM*2 tRWD1 2 11 ns Figure 2.11 to Figure 2.35 Other than the above 0 10 ns Read strobe delay time tRSD 1/2tCKcyc 1/2tCKcyc + 10 ns Figure 2.11 to Figure 2.18 Read data setup time 1*3 High-drive output tRDS1 1/2tCKcyc + 4 — ns Figure 2.11 to Figure 2.17 Normal output 1/2tCKcyc + 7 — ns Read data setup time 2*3 High-drive output tRDS2 6.6 — ns Figure 2.19 to Figure 2.22, Figure 2.27 to Figure 2.29 Read data setup time 3*3 High-drive output tRDS3 1/2tCKcyc + 4 — ns Figure 2.18 Normal output 1/2tCKcyc + 7 — ns Read data hold time 1 tRDH1 0 — ns Figure 2.11 to Figure 2.17 Read data hold time 2 tRDH2 2.5 — ns Figure 2.19 to Figure 2.22, Figure 2.27 to Figure 2.29 Read data hold time 3 tRDH3 0 — ns Figure 2.18 Write enable delay time 1 tWED1 1/2tCKcyc 1/2tCKcyc + 10 ns Figure 2.11 to Figure 2.16 Write enable delay time 2 tWED2 — 11 ns Figure 2.17 Write data delay time 1 tWDD1 — 11 ns Figure 2.11 to Figure 2.17 RZ/T2M Datasheet 2. Electrical Characteristics R01DS0383EJ0130 Rev.1.30 Mar 13, 2026 Page 58 of 128 |
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