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RZ/T2M Scheda tecnica(PDF) 9 Page - Renesas Technology Corp

Il numero della parte RZ/T2M
Spiegazioni elettronici  RZ Arm-based High-end 32 & 64-bit MPUs
PDF  128 Pages
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Produttore elettronici  RENESAS [Renesas Technology Corp]
Homepage  http://www.renesas.com
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RZ/T2M Scheda tecnica(HTML) 9 Page - Renesas Technology Corp

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Table 1.11
Safety (2 of 2)
Feature
Functional description
Clock monitor circuit (CLMA)
● Monitors the abnormal output clock frequency from the input clock (main clock oscillator),
PLL circuit, or low-speed on-chip oscillator.
● Input clock oscillation stop detection: Available
Data operation circuit (DOC)
The function to compare, add, or subtract 16-bit data
Isolated peripherals
● Safety dedicated peripherals are available:
– GPT: 4 ch
– SCI: 1 ch
– IIC: 1 ch
– SPI: 1 ch
– CRC: 1 unit
– RTC: 1 unit
– GPIO: Sharable with normal GPIO
– On-chip system SRAM with ECC
● They are mapped independently from normal peripherals so that access protection can be
done by EL2 MPU.
Table 1.12
Security
Feature
Functional description
Security*1
● Secure boot
● JTAG authentication*2
● SCI/USB boot disable
● Cryptographic accelerators
– Symmetric Cipher: AES 128/192/256 bits with CBC/ECB/CTR/GCM/XTS
– Asymmetric Cipher: ECC 256 bits, RSA 1024/2048/3072 bits, RSAES-OAEP
– Hash: SHA-1, SHA-2
– Message authentication: HMAC, CMAC, GMAC
– Signature algorithms: ECDSA with NIST P-256, RSASSA-PSS, RSASSA-PKCS1
● TRNG
Note 1. For details, contact our sales representative.
Note 2. Authentication by plaintext is available in non-security support product.
Table 1.13
Debug
Feature
Functional description
Debugging interface
● CoreSight architecture designed by Arm
● Debugging function by the JTAG/SWD interface, and trace function by the trace port
interface
Table 1.14
Others
Feature
Functional description
Power supply voltage
VDD = 1.1 V (Core)
VCC18 = 1.8 V (PLL, USB, ADC, TSU)
VCC33 = 3.3 V (I/O, USB)
VCC1833 = 1.8 V (RGMII, xSPI) or 3.3 V (RMII/MII, xSPI*1)
Operating temperature
Tj = −40 to +125°C
Packages
320 pin FBGA 17 × 17 mm, 0.8-mm pitch
225 pin FBGA 13 × 13 mm, 0.8-mm pitch
176 pin LQFP (Exposed Die Pad) 24 × 24 mm, 0.5-mm pitch
128 pin LQFP (Exposed Die Pad) 20 × 14 mm, 0.5-mm pitch
Note 1. Maximum xSPI clock frequency is 75 MHz at 3.3 V.
RZ/T2M Datasheet
1. Overview
R01DS0383EJ0130 Rev.1.30
Mar 13, 2026
Page 9 of 128



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