RZSLASHT2M datasheet(90/128 Pages) RENESAS

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PCLKH

tGTEW

External trigger

Figure 2.48

GPT external trigger input timing

2.5.5.6

POEG Timing

Table 2.30

POEG timing

Parameter

Symbol

Min.

Max.

Unit*1

Reference figure

POEG

GTETRGn input pulse width (n = A to D)

tPOEGW

2.5

—

tPHcyc

Figure 2.49

Output

disable time

Input level detection of the

GTETRGn pin (via flag)

tPOEGDI

—

3 × PCLKH

+ 0.1

µs

Figure 2.50

Detection of the output stopping

signal from GPT (dead time

error, simultaneous high output,

or simultaneous low output)

tPOEGDO

—

0.1

µs

Figure 2.51

tPOEGDS

—

PCLKH +

0.1

µs

Figure 2.52

Oscillation stop detection

tPOEGDOS

—

µs

Figure 2.53

Note 1. tPHcyc: PCLKH cycle (LLPP channels), PCLKL cycle (Other channels)

PCLKL, PCLKH

GTETRGn input

(n = A to D)

tPOEGW

Figure 2.49

POEG input timing

Outputs disabled

GPT PWM output pins

POEGGn.PIDF flag

(n = A to D)

GTETRGn input

(n = A to D)

tPOEGW

tPOEGDI

Figure 2.50

Output disable time for POEG via detection flag in response to the input level detection of the

GTETRGn pin

RZ/T2M Datasheet

2. Electrical Characteristics

R01DS0383EJ0130 Rev.1.30

Mar 13, 2026

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