M32CSLASH8B datasheet(64/406 Pages) RENESAS

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M32C/8B Group

8. Bus

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 47 of 385

8.2

Bus Control

Described below are the signals required to access external devices and the bus timing. The signals are available in

memory expansion mode and microprocessor mode only.

8.2.1

Address Bus and Data Bus

Address bus is the signals to access 16-Mbyte space, and consists of 24 control pins; A0 to A22 and A23. A23

is an inverse output signal of the highest-order address bit.

Data bus is the signals for data input and output. The DS register selects either an 8-bit data bus width from D0

to D7 or a 16-bit data bus width from D0 to D15 for each external space. When a high-level (“H”) signal is

applied to the BYTE pin, the data bus accessing the external space 3 is 8 bits wide after reset. When a low-level

(“L”) signal is applied to the BYTE pin, the data bus accessing the external space 3 is 16 bits wide.

When changing single-chip mode to memory expansion mode, the address bus value is undefined until the

MCU accesses an external space.

8.2.2

Chip-Select Output

Chip-select outputs share pins with address bus, A20 to A22 and A23. Bits PM11 and PM10 in the PM1 register

determine the CS areas to be accessed and the number of chip-select outputs. Maximum of four chip-select

outputs are provided.

In microprocessor mode, no chip-select signal is output after reset. Only A23, however, can perform as a chip-

select output.

The CSi pin (i = 0 to 3) outputs an “L” signal while accessing its corresponding external space. An “H” signal is

output while the MCU is accessing other external spaces. Figure 8.2 shows an example of address bus and chip-

select outputs (separate bus).

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