M32CSLASH8B datasheet(76/406 Pages) RENESAS

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Under development

M32C/8B Group

8. Bus

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 59 of 385

Figure 8.11

RD Output Signal Extended by RDY Input

8.2.7

HOLD Input

The HOLD input signal is used to transfer ownership of the bus from the CPU to external devices. When a low-

level (“L”) signal is applied to the HOLD pin, the MCU enters a hold state after the bus access in progress is

completed. While the HOLD pin is held “L”, the MCU remains in a hold state and the HLDA pin outputs an

“L” signal. Table 8.8 lists the MCU states in hold state.

Bus is used in the following priority order: HOLD, DMAC, CPU.

Table 8.8

MCU States in Hold State

NOTE:

1. When the PM22 bit in the PM2 register is set to 1 (selects the on-chip oscillator clock as count source for the

watchdog timer), watchdog timer does not stop.

Item

State

Clock generation circuits

Operating (oscillating)

CPU

Stopped

Internal peripheral circuits

Operating

(Watchdog timer is stopped)(1)

RD, WR, A0 to A22, A23, D0 to D15, CS0 to CS3, BHE

High-impedance

HLDA

Outputs “L”

ALE

Outputs “L”

Programmable I/O ports

Maintains the same state as when “L” is input to HOLD pin.

- Separate bus (bus cycle is 1 φ + 2 φ)

BCLK

CSi(1)

RDY

Timing to input RDY signal

- Multiplexed bus (bus cycle is 2 φ + 2 φ)

BCLK

CSi(1)

RDY

tsu(RDY-BCLK)

Timing to input RDY signal

NOTE:

1. Chip-select output (CSi) may be extended depending on the CPU state such as the instruction queue buffer.

tsu(RDY-BCLK): RDY input setup time

: Wait states inserted by RDY input

i = 0 to 3

tsu(RDY-BCLK)

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