M32CSLASH8B datasheet(80/406 Pages) RENESAS

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Under development

M32C/8B Group

8. Bus

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 63 of 385

Figure 8.13

PWCR1 Register

Symbol

PWCR1

Address

004Dh

After Reset

0001 0001b

b7 b6 b5 b4

Page Mode Wait Control Register 1

Bit Symbol

Bit Name

PWCR100

NOTE:

1. When page mode control is enabled, set the EWCRi6 bit in the EWCRi register (i = 0 to 3) to 0 (add no recovery

cycle when accessing external space i ).

Function

External space 2

subsequent access

wait select bits

PWCR101

PWCR102

b2 b1 b0

0 0 1: 1 φ + 1 φ

0 1 0: 1 φ + 2 φ

0 1 1: 1 φ + 3 φ

1 0 0: 1 φ + 4 φ

Do not set to values other than the above.

PWCR103

PWCR105

PWCR104

PWCR106

PWCR107

External space 2

page mode control enable bit

0: Page mode control disabled

1: Page mode control enabled(1)

External space 3

subsequent access

wait select bits

b6 b5 b4

0 0 1: 1 φ + 1 φ

0 1 0: 1 φ + 2 φ

0 1 1: 1 φ + 3 φ

1 0 0: 1 φ + 4 φ

Do not set to values other than the above.

External space 3

page mode control enable bit

0: Page mode control disabled

1: Page mode control enabled(1)

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