M32CSLASH8B datasheet(86/406 Pages) RENESAS

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M32C/8B Group

9. Clock Generation Circuits

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 69 of 385

Figure 9.4

MCD Register

b7 b6 b5 b4

Main Clock Division Register(1)

Symbol

MCD

Address

000Ch

Bit Symbol

Bit Name

MCD0

After Reset

XXX0 1000b

NOTES:

1. Set the MCD register after the PRC0 bit in the PRCR register is set to 1 (write enable).

2. When stop mode or low-power consumption mode is entered, bits MCD4 to MCD0 become 01000b.

Bits MCD4 to MCD0, however, do not become 01000b if the CM05 bit in the CM0 register is set to 1 (main clock stops) while

the CM21 bit in the CM2 register is set to 1.

Function

Main clock division rate

select bits(2)

MCD1

MCD2

b4 b3 b2 b1 b0

1 0 0 1 0: Divide-by-1 (no division) mode

0 0 0 1 0: Divide-by-2 mode

0 0 0 1 1: Divide-by-3 mode

0 0 1 0 0: Divide-by-4 mode

0 0 1 1 0: Divide-by-6 mode

0 1 0 0 0: Divide-by-8 mode

0 1 0 1 0: Divide-by-10 mode

0 1 1 0 0: Divide-by-12 mode

0 1 1 1 0: Divide-by-14 mode

0 0 0 0 0: Divide-by-16 mode

Do not set to values other than the above

MCD3

MCD4

−

(b7-b5)

−

Reserved bits

Read as undefined value

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