M32CSLASH8B datasheet(109/406 Pages) RENESAS

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Under development

M32C/8B Group

9. Clock Generation Circuits

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 92 of 385

9.5.3.2

Pin States in Stop Mode

Table 9.9 lists pin states in stop mode.

Table 9.9

Pin States in Stop Mode

9.5.3.3

Exiting Stop Mode

Stop mode is exited by the hardware reset, NMI interrupt, voltage monitor interrupt, or peripheral function

interrupts. The following are the peripheral function interrupts that can be used to exit stop mode.

• Key input interrupt

• INT interrupt

• Timer A and timer B interrupts

(Available when the timer counts external pulse having 100-Hz frequency or lower in event counter mode)

When only the hardware reset, NMI interrupt, or voltage monitor interrupt is used to exit stop mode, set bits

ILVL2 to ILVL0 in the Interrupt Control Registers for all the peripheral function interrupts to 000b (interrupt

disabled) before setting the CM10 bit in the CM1 register to 1 (all clocks stop).

If the voltage applied to pins VCC1 and VCC2 drops below 3.0 V in stop mode, exit stop mode by the hardware

reset after the voltage has satisfied the recommended operating conditions.

Memory Expansion Mode

Microprocessor Mode

Single-Chip Mode

Address Bus, Data Bus, CS0 to CS3, BHE

Maintain the state immediately

before entering stop mode

RD, WR, WRL, WRH

“H”

HLDA, BCLK

“H”

ALE

“H”

Ports

Maintain the state immediately before entering stop mode

CLKOUT

When fC is selected

“H”

When f8, f32 are selected

The clock is stopped and holds the level immediately before

entering stop mode

XIN

Placed in a high-impedance state

XOUT

“H”

XCIN, XCOUT

Placed in a high-impedance state

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