M32CSLASH8B datasheet(118/406 Pages) RENESAS

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M32C/8B Group

11. Interrupts

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 101 of 385

Table 11.3

Relocatable Vector Tables (2/2)

NOTES:

1. These are the addresses offset from the base address set in the INTB register.

2. The I flag can not disable this interrupt.

3. In I2C mode, NACK, ACK, or start/stop condition detection can be the interrupt sources.

4. The IFSR6 bit in the IFSR register selects either UART0 or UART3. The IFSR7 bit selects either UART1 or

UART4.

Interrupt Source

Vector Table Address

Address (L) to Address (H)(1)

Software

Interrupt Number

Reference

Bus conflict detection,

Start condition detection/

Stop condition detection

(UART2)(3)

+156 to +159 (009Ch to 009Fh)

Serial interfaces

Bus conflict detection,

Start condition detection/

Stop condition detection

(UART3 or UART0)(4)

+160 to +163 (00A0h to 00A3h)

Bus conflict detection,

Start condition detection/

Stop condition detection

(UART4 or UART1)(4)

+164 to +167 (00A4h to 00A7h)

A/D0

+168 to +171 (00A8h to 00ABh)

A/D converter

Key input

+172 to +175 (00ACh to 00AFh)

Interrupts

Reserved space

+176 to +255 (00B0h to 00FFh)

44 to 63

−

INT instruction(2)

+0 to +3 (0000h to 0003h) to

+252 to +255 (00FCh to 00FFh)

0 to 63

Interrupts

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