XIO2001 datasheet(34/131 Pages) TI

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3.4.4

PCI Bus External Arbiter

3.4.5

MSI Messages Generated from the Serial IRQ Interface

XIO2001 PCI Express™ to PCI Bus Translation Bridge

SCPS212B – MAY 2009 – REVISED JULY 2009

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To enable the clock run function, terminal CLKRUN_EN is asserted high. Then, terminal GPIO0 is enabled

as the CLKRUN signal. An external pullup resistor must be provided to prevent the CLKRUN signal from

floating To verify the operational status of the PCI bus clocks, bit 0 (SEC_CLK_STATUS) in the clock run

status register at offset DAh (see Section 4.68) is read.

Since the bridge has several unique features associated with the PCI bus interface, the system designer

must consider the following interdependencies between these features and the CLKRUN feature:

1. If the system designer chooses to generate the PCI bus clock externally, then the CLKRUN mode of

the bridge must be disabled. The central resource function within the bridge only operates as a

CLKRUN master and does not support the CLKRUN slave mode.

2. If the central resource function has stopped the PCI bus clocks, then the bridge still detects INTx state

changes and will generate and send PCI Express messages upstream.

3. If the serial IRQ interface is enabled and the central resource function has stopped the PCI bus clocks,

then any PCI bus device that needs to report an IRQ interrupt asserts CLKRUN to start the bus clocks.

4. When a PCI bus device asserts CLKRUN, the central resource function turns on PCI bus clocks for a

minimum of 512 cycles.

5. If the serial IRQ function detects an IRQ interrupt, then the central resource function keeps the PCI bus

clocks running until the IRQ interrupt is cleared by software.

6. If the central resource function has stopped the PCI bus clocks and the bridge receives a downstream

transaction that is forwarded to the PCI bus interface, then the bridge asserts CLKRUN to start the bus

clocks.

7. The central resource function is reset by PCI bus reset (PRST) assuring that clocks are present during

PCI bus resets.

The bridge supports an external arbiter for the PCI bus. Terminal (EXT_ARB_EN), when asserted high,

enables the use of an external arbiter.

When an external arbiter is enabled, GNT0 is connected to the external arbiter as the REQ for the bridge.

Likewise, REQ0 is connected to the external arbiter as the GNT for the bridge.

When properly configured, the bridge converts PCI bus serial IRQ interrupts into PCI Express message

signaled interrupts (MSI). classic PCI configuration register space is provided to enable this feature. The

following list identifies the involved configuration registers:

1. Command register at offset 04h, bit 2 (MASTER_ENB) is asserted (see Table 4-2).

2. MSI message control register at offset 52h, bits 0 (MSI_EN) and 6:4 (MM_EN) enable single and

multiple MSI messages, respectively (see Section 4.42).

3. MSI message address register at offsets 54h and 58h specifies the message memory address. A

nonzero address value in offset 58h initiates 64-bit addressing (see Section 4.37 and Section 4.44).

4. MSI message data register at offset 5Ch specifies the system interrupt message (see Section 4.45).

5. Serial IRQ mode control register at offset E0h specifies the serial IRQ bus format (see Section 4.72).

6. Serial IRQ edge control register at offset E2h selects either level or edge mode interrupts (see

Section 4.73).

7. Serial IRQ status register at offset E4h reports level mode interrupt status (see Section 4.74).

A PCI Express MSI is generated based on the settings in the serial IRQ edge control register. If the

system is configured for edge mode, then an MSI message is sent when the corresponding serial IRQ

interface sample phase transitions from low to high. If the system is configured for level mode, then an

MSI message is sent when the corresponding IRQ status bit in the serial IRQ status register changes from

low to high.

Feature/Protocol Descriptions

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