XIO2001 datasheet(67/131 Pages) TI

67 / 131 page

4.41 Next Item Pointer Register

4.42 MSI Message Control Register

4.43 MSI Message Lower Address Register

XIO2001 PCI Express™ to PCI Bus Translation Bridge

www.ti.com

SCPS212B – MAY 2009 – REVISED JULY 2009

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge.

This register reads 70h pointing to the subsystem ID capabilities registers.

PCI register offset:

51h

Read-only

Default value:

70h

BIT NUMBER

RESET STATE

This register controls the sending of MSI messages. See Table 4-21 for a complete description of the

PCI register offset:

52h

Read-only, Read/Write

Default value:

0088h

BIT NUMBER

RESET STATE

Table 4-21. MSI Message Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:8

RSVD

Reserved. Returns 00h when read.

64CAP

64-bit message capability. This bit is read-only 1b indicating that the bridge supports 64-bit

MSI message addressing.

6:4

MM_EN

Multiple message enable. This bit indicates the number of distinct messages that the

bridge is allowed to generate.

000 = 1 message (default)

001 = 2 messages

010 = 4 messages

011 = 8 messages

100 = 16 messages

101 = Reserved

110 = Reserved

111 = Reserved

3:1

MM_CAP

Multiple message capabilities. This field indicates the number of distinct messages that

bridge is capable of generating. This field is read-only 100b indicating that the bridge can

signal 1 interrupt for each IRQ supported on the serial IRQ stream up to a maximum of 16

unique interrupts.

MSI_EN

MSI enable. This bit enables MSI interrupt signaling. MSI signaling must be enabled by

software for the bridge to signal that a serial IRQ has been detected.

0 = MSI signaling is prohibited (default)

1 = MSI signaling is enabled

This register contains the lower 32 bits of the address that a MSI message writes to when a serial IRQ is

detected. See Table 4-22 for a complete description of the register contents.

PCI register offset:

54h

Read-only, Read/Write

Default value:

0000 0000h

Submit Documentation Feedback

Classic PCI Configuration Space

XIO2001 Scheda tecnica(PDF) 67 Page - Texas Instruments

XIO2001 Scheda tecnica(HTML) 67 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL