XIO2001 datasheet(76/131 Pages) TI

76 / 131 page

4.58 Serial-Bus Control and Status Register

XIO2001 PCI Express™ to PCI Bus Translation Bridge

SCPS212B – MAY 2009 – REVISED JULY 2009

www.ti.com

Table 4-31. Serial-Bus Slave Address Register Descriptions

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:1(1)

SLAVE_ADDR

Serial-bus slave address. This 7-bit field is the slave address for a serial-bus read or write

transaction. The default value for this field is 000 0000b.

0(1)

RW_CMD

Read/write command. This bit determines if the serial-bus cycle is a read or a write cycle.

0 = A single byte write is requested (default).

1 = A single byte read is requested.

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

The serial-bus control and status register controls the behavior of the serial-bus interface. This register

also provides status information about the state of the serial bus. See Table 4-32 for a complete

description of the register contents.

PCI register offset:

B3h

Read-only, Read/Write, Read/Clear

Default value:

00h

BIT NUMBER

RESET STATE

Table 4-32. Serial-Bus Control and Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7(1)

PROT_SEL

Protocol select. This bit selects the serial-bus address mode used.

0 = Slave address and word address are sent on the serial-bus (default)

1 = Only the slave address is sent on the serial-bus

RSVD

Reserved. Returns 0b when read.

5(1)

REQBUSY

Requested serial-bus access busy. This bit is set when a software-initiated serial-bus cycle

is in progress.

0 = No serial-bus cycle

1 = Serial-bus cycle in progress

4(1)

ROMBUSY

Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the bridge

is downloading register defaults from a serial EEPROM.

0 = No EEPROM activity

1 = EEPROM download in progress

3(1)

SBDETECT

RWU

Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the bridge

is downloading register defaults from a serial EEPROM.

Note: A serial EEPROM is only detected once following PERST.

0 = No EEPROM present, EEPROM load process does not happen. GPIO4//SCL and

GPIO3//SDA terminals are configured as GPIO signals.

1 = EEPROM present, EEPROM load process takes place. GPIO4//SCL and

GPIO3//SDA terminals are configured as serial-bus signals.

2(1)

SBTEST

Serial-bus test. This bit is used for internal test purposes. This bit controls the clock source

for the serial interface clock.

0 = Serial-bus clock at normal operating frequency ~ 60 kHz (default)

1 = Serial-bus clock frequency increased for test purposes ~ 4 MHz

1(1)

SB_ERR

RCU

Serial-bus error. This bit is set when an error occurs during a software-initiated serial-bus

cycle.

0 = No error

1 = Serial-bus error

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

Classic PCI Configuration Space

Submit Documentation Feedback

XIO2001 Scheda tecnica(PDF) 76 Page - Texas Instruments

XIO2001 Scheda tecnica(HTML) 76 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL