PCF8533USLASH2DASLASH2 datasheet(18/45 Pages) NXP

18 / 45 page

PCF8533_4

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Product data sheet

Rev. 04 — 5 March 2010

18 of 45

NXP Semiconductors

PCF8533

Universal LCD driver for low multiplex rates

I2C-bus interface

8.1 Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

By connecting pin SDAACK to pin SDA on the PCF8533, the SDA line becomes fully

I2C-bus compatible. Having the acknowledge output separated from the serial data line is

advantageous in Chip-On-Glass (COG) applications. In COG applications where the track

resistance from the SDAACK pin to the system SDA line can be significant, a potential

divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track

resistance. It is possible that during the acknowledge cycle the PCF8533 will not be able

to create a valid logic 0 level. By separating the SDA input from the output the device

could be used in a mode that ignores the acknowledge bit. In COG applications where the

acknowledge cycle is required, it is necessary to minimize the track resistance from the

SDAACK pin to the system SDA line to guarantee a valid LOW level.

The following definition assumes SDA and SDAACK are connected and refers to the pair

as SDA.

8.1.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal; see Figure 11.

8.1.1.1

START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is defined as the START condition (S);

see Figure 12. A LOW-to-HIGH transition of the data line while the clock is HIGH is

defined as the STOP condition (P).

Fig 11. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

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