PCF8533USLASH2DASLASH2 datasheet(29/45 Pages) NXP

29 / 45 page

PCF8533_4

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Product data sheet

Rev. 04 — 5 March 2010

29 of 45

NXP Semiconductors

PCF8533

Universal LCD driver for low multiplex rates

[1]

Typical output duty cycle of 50 %.

[2]

All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an

input voltage swing of VSS to VDD.

[3]

The corresponding frame frequency is

Pins SCL and SDA

tBUF

bus free time between a STOP and START condition

1.3

μs

tSU;STO

set-up time for STOP condition

0.6

μs

tHD;STA

hold time (repeated) START condition

0.6

μs

tSU;STA

set-up time for a repeated START condition

0.6

μs

rise time of both SDA and SCL signals

0.3

μs

fall time of both SDA and SCL signals

0.3

μs

capacitive load for each bus line

400

tw(spike)

spike pulse width

on bus

Table 17.

Dynamic characteristics …continued

VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

clk 24

⁄

Fig 20. Driver timing waveforms

001aag591

tPD(drv)

tSYNC_NL

tPD(SYNC_N)

CLK

SYNC

BP0 to BP3,

and S0 to S79

tclk(H)

tclk(L)

1 / fCLK

0.7 VDD

0.3 VDD

0.7 VDD

0.3 VDD

0.5 V

(VDD = 5 V)

0.5 V

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