PCF8533USLASH2DASLASH2 datasheet(28/45 Pages) NXP

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PCF8533_4

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Product data sheet

Rev. 04 — 5 March 2010

28 of 45

NXP Semiconductors

PCF8533

Universal LCD driver for low multiplex rates

12. Dynamic characteristics

Tamb =30 °C; 1:4 multiplex; fclk(ext) = 1.536 kHz; all RAM written with logic 1; no display connected.

Fig 19. Typical IDD(LCD) with respect to VLCD

001aal524

VLCD (V)

IDD(LCD)

(

μA)

Table 17.

Dynamic characteristics

VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Clock

fclk(int)

internal clock frequency

[1][3] 960

1536

3046

fclk(ext)

external clock frequency

[1][3] 797

1536

3046

tclk(H)

HIGH-level clock time

130

μs

tclk(L)

LOW-level clock time

130

μs

rise time

--ns

fall time

Synchronization: input pin SYNC

tPD(SYNC_N)

SYNC propagation delay

tSYNC_NL

SYNC LOW time

μs

Outputs: pins BP0 to BP3 and S0 to S79

tPD(drv)

driver propagation delay

VLCD = 5 V

μs

I2C-bus: timing[2]; see Figure 21

Pin SCL

fSCL

SCL clock frequency

400

kHz

tLOW

LOW period of the SCL clock

1.3

μs

tHIGH

HIGH period of the SCL clock

0.6

μs

Pin SDA

tSU;DAT

data set-up time

100

tHD;DAT

data hold time

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