MSP430F5529 datasheet(49/115 Pages) TI

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2.0

1.8

SupplyVoltage-V

ThenumberswithinthefieldsdenotethesupportedPMMCOREVxsettings.

2.2

2.4

3.6

0,1,2,3

0,1,2

0,1

1,2,3

1,2

2,3

MSP430F551x

MSP430F552x

www.ti.com

SLAS590D – OCTOBER 2009 – REVISED APRIL 2010

Recommended Operating Conditions

MIN

NOM

MAX

UNIT

PMMCOREVx = 0

1.8

3.6

PMMCOREVx = 0, 1

2.0

3.6

Supply voltage during program execution and flash

VCC

programming(AVCC = DVCC1/2 = DVCC)

(1)

PMMCOREVx = 0, 1, 2

2.2

3.6

PMMCOREVx = 0, 1, 2, 3

2.4

3.6

PMMCOREVx = 0

1.8

3.6

PMMCOREVx = 0, 1

2.0

3.6

Supply voltage during USB operation, USB PLL disabled

USB_EN = 1, UPLLEN = 0

PMMCOREVx = 0, 1, 2

2.2

3.6

VCC, USB

PMMCOREVx = 0, 1, 2, 3

2.4

3.6

PMMCOREVx = 2

2.2

3.6

Supply voltage during USB operation, USB PLL enabled(2)

USB_EN = 1, UPLLEN = 1

PMMCOREVx = 2, 3

2.4

3.6

VSS

Supply voltage (AVSS = DVSS1/2 = DVSS)

Operating free-air temperature

I version

–40

°C

Operating junction temperature

I version

–40

°C

CVCORE

Capacitor at VCORE

470

CDVCC/

Capacitor ratio of DVCC to VCORE

CVCORE

PMMCOREVx = 0

1.8 V

≤ VCC ≤ 3.6 V

8.0

(default condition)

PMMCOREVx = 1

12.0

Processor frequency (maximum MCLK frequency)(3)

2.0 V

≤ VCC ≤ 3.6 V

fSYSTEM

MHz

(see Figure 1)

PMMCOREVx = 2

20.0

2.2 V

≤ VCC ≤ 3.6 V

PMMCOREVx = 3

25.0

2.4 V

≤ VCC ≤ 3.6 V

fSYSTEM_USB

Minimum processor frequency for USB operation

1.5

MHz

USB_wait

Wait state cycles during USB operation

cycles

(1)

It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be

tolerated during power up and operation.

(2)

USB operation with USB PLL enabled requires PMMCOREVx

≥ 2 for proper operation.

(3)

Modules may have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.

Figure 1. Maximum System Frequency

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