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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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MSP430F5529 Scheda tecnica(PDF) 29 Page - Texas Instruments |
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MSP430F5529 Scheda tecnica(HTML) 29 Page - Texas Instruments |
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29 / 115 page  MSP430F551x MSP430F552x www.ti.com SLAS590D – OCTOBER 2009 – REVISED APRIL 2010 TA0 TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. It can support multiple capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 13. TA0 Signal Connections INPUT PIN NUMBER DEVICE MODULE MODULE DEVICE OUTPUT PIN NUMBER MODULE INPUT INPUT OUTPUT OUTPUT BLOCK RGC/ZQE PN RGC/ZQE PN SIGNAL SIGNAL SIGNAL SIGNAL 18/H2-P1.0 21-P1.0 TA0CLK TACLK ACLK ACLK (internal) Timer NA NA SMCLK SMCLK (internal) 18/H2-P1.0 21-P1.0 TA0CLK TACLK 19/H3-P1.1 22-P1.1 TA0.0 CCI0A 19/H3-P1.1 22-P1.1 DVSS CCI0B CCR0 TA0 TA0.0 DVSS GND DVCC VCC 20/J3-P1.2 23-P1.2 TA0.1 CCI1A 20/J3-P1.2 23-P1.2 ADC12 ADC12 CBOUT (internal)(1) (internal)(1) CCI1B (internal) ADC12SHSx = ADC12SHSx = CCR1 TA1 TA0.1 {1} {1} DVSS GND DVCC VCC 21/G4-P1.3 24-P1.3 TA0.2 CCI2A 21/G4-P1.3 24-P1.3 ACLK CCI2B (internal) CCR2 TA2 TA0.2 DVSS GND DVCC VCC 22/H4-P1.4 25-P1.4 TA0.3 CCI3A 22/H4-P1.4 25-P1.4 DVSS CCI3B CCR3 TA3 TA0.3 DVSS GND DVCC VCC 23/J4-P1.5 26-P1.5 TA0.4 CCI4A 23/J4-P1.5 26-P1.5 DVSS CCI4B CCR4 TA4 TA0.4 DVSS GND DVCC VCC (1) Only on devices with ADC. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 29 |
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