MSP430F5529 datasheet(23/115 Pages) TI

23 / 115 page

MSP430F551x

MSP430F552x

www.ti.com

SLAS590D – OCTOBER 2009 – REVISED APRIL 2010

RAM Memory

The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,

however all data is lost. Features of the RAM memory include:

•

RAM memory has n sectors. The size of a sector can be found in the Memory Organization section.

•

Each sector 0 to n can be complete disabled, however data retention is lost.

•

Each sector 0 to n automatically enters low power retention mode when possible.

•

For Devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.

Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all

instructions. For complete module descriptions, see the MSP430x5xx Family User's Guide, literature number

SLAU208.

Digital I/O

There are up to eight 8-bit I/O ports implemented: For 80 pin options, P1, P2, P3, P4, P5, P6, and P7 are

complete. P8 is reduced to 3-bit I/O. For 64 pin options, P3 and P5 are reduced to 5-bit I/O and 6-bit I/O,

respectively. P7 and P8 are completely removed. Port PJ contains four individual I/O ports, common to all

devices.

•

All individual I/O bits are independently programmable.

•

Any combination of input, output, and interrupt conditions is possible.

•

Pullup or pulldown on all ports is programmable.

•

Drive strength on all ports is programmable.

•

Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2.

•

Read/write access to port-control registers is supported by all instructions.

•

Ports can be accessed byte-wise (P1 through P8) or word-wise in pairs (PA through PD).

Submit Documentation Feedback

MSP430F5529 Scheda tecnica(PDF) 23 Page - Texas Instruments