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MSP430F5529 Scheda tecnica(PDF) 85 Page - Texas Instruments |
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MSP430F5529 Scheda tecnica(HTML) 85 Page - Texas Instruments |
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85 / 115 page ![]() P5.3/XT2OUT P5SEL.3 1 0 P5DIR.3 P5IN.3 EN ModuleXIN 1 0 ModuleXOUT P5OUT.3 1 0 DV SS DV CC P5REN.3 PadLogic 1 P5DS.3 0:Lowdrive 1:Highdrive D Bus Keeper ToXT2 MSP430F551x MSP430F552x www.ti.com SLAS590D – OCTOBER 2009 – REVISED APRIL 2010 Port P5, P5.3, Input/Output With Schmitt Trigger Table 53. Port P5 (P5.2, P5.3) Pin Functions CONTROL BITS/SIGNALS(1) PIN NAME (P5.x) x FUNCTION P5DIR.x P5SEL.2 P5SEL.3 XT2BYPASS P5.2/XT2IN 2 P5.2 (I/O) I: 0; O: 1 0 X X XT2IN crystal mode(2) X 1 X 0 XT2IN bypass mode(2) X 1 X 1 P5.3/XT2OUT 3 P5.3 (I/O) I: 0; O: 1 0 X X XT2OUT crystal mode(3) X 1 X 0 P5.3 (I/O)(3) X 1 X 1 (1) X = Don't care (2) Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal mode or bypass mode. (3) Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as general-purpose I/O. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 85 |
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