MSP430F5529 datasheet(67/115 Pages) TI

67 / 115 page

MSP430F551x

MSP430F552x

www.ti.com

SLAS590D – OCTOBER 2009 – REVISED APRIL 2010

USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(see Note

(1), Figure 13 and Figure 14)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

1.8 V

PMMCOREV = 0

3.0 V

tSTE,LEAD

STE lead time, STE low to clock

2.4 V

PMMCOREV = 3

3.0 V

1.8 V

PMMCOREV = 0

3.0 V

tSTE,LAG

STE lag time, Last clock to STE high

2.4 V

PMMCOREV = 3

3.0 V

1.8 V

PMMCOREV = 0

3.0 V

tSTE,ACC

STE access time, STE low to SOMI data out

2.4 V

PMMCOREV = 3

3.0 V

1.8 V

PMMCOREV = 0

3.0 V

STE disable time, STE high to SOMI high

tSTE,DIS

impedance

2.4 V

PMMCOREV = 3

3.0 V

1.8 V

PMMCOREV = 0

3.0 V

tSU,SI

SIMO input data setup time

2.4 V

PMMCOREV = 3

3.0 V

1.8 V

PMMCOREV = 0

3.0 V

tHD,SI

SIMO input data hold time

2.4 V

PMMCOREV = 3

3.0 V

UCLK edge to SOMI valid,

1.8 V

CL = 20 pF

3.0 V

PMMCOREV = 0

tVALID,SO

SOMI output data valid time(2)

UCLK edge to SOMI valid,

2.4 V

CL = 20 pF

3.0 V

PMMCOREV = 3

1.8 V

CL = 20 pF

PMMCOREV = 0

3.0 V

tHD,SO

SOMI output data hold time(3)

2.4 V

CL = 20 pF

PMMCOREV = 3

3.0 V

(1)

fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).

For the master's parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached slave.

(2)

Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing

diagrams in Figure 11 and Figure 12.

(3)

Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in

Figure 11 and Figure 12.

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