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MPC8378E Scheda tecnica(PDF) 114 Page - Freescale Semiconductor, Inc |
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MPC8378E Scheda tecnica(HTML) 114 Page - Freescale Semiconductor, Inc |
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114 / 127 page  MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 114 Freescale Semiconductor Clocking 22.3 Suggested PLL Configurations Table 76 shows suggested PLL configurations for different input clocks (LBCM = 0). 00 0100 04:1 2 01 0100 04:1 4 10 0100 04:1 8 Note: 1 Core VCO frequency = Core frequency × VCO divider. Note that VCO divider has to be set properly so that the core VCO frequency is in the range of 800–1600 MHz. Table 76. Example Clock Frequency Combinations eLBC 1 e300 Core 1 Ref 1 LBCM DDRCM SVCOD SPMF Sys VCO 1,2 CSB 1,3 DDR data rate 1,4 /2 /4 /8 × 1 × 1.5 × 2 × 2.5 × 3 25.0 0 1 2 5 500 125 250 62.5 31.3 15.6 ———— 375 25.0 0 1 2 6 600 150 300 75 6 37.5 18.8 — — — 375 450 33.3 0 1 2 5 667 167 333 83.3 6 41.6 20.8 — — 333 416 500 33.3 0 1 2 4 533 133 267 66.7 33.3 16.7 — — — 333 400 48.0 0 1 2 3 576 144 288 72 6 36 18 — — — 360 432 66.7 0 1 2 2 533 133 266 66.7 33.3 16.7 — — — 333 400 25.0 0 0 4 8 800 200 200 100 6 50 25 — — 400 500 600 33.3 0 0 2 8 533 266.7 267 133 6 66.7 33.3 — 400 533 667 800 50.0 0 0 4 4 800 200 200 100 6 50 25 — — 400 500 600 50.0 0 0 2 8 800 400 400 5 — 100 6 50 — 600 800 — — 66.7 0 0 2 4 533 266.7 267 133 6 66.7 33.3 — 400 533 667 800 66.7 0 0 2 5 667 333 333 — 83.3 6 41.6 333 500 667 — — 66.7 0 0 2 6 800 400 400 5 — 100 6 50 400 600 800 — — Note: 1 Values in MHz. 2 System PLL VCO range: 400–800 MHz. 3 CSB frequencies less than 133 MHz will not support Gigabit Ethernet rates. 4 Minimum data rate for DDR2 is 250 MHz and for DDR1 is 167 MHz. 5 Applies to DDR2 only. 6 Applies to eLBC PLL-enabled mode only. Table 75. e300 Core PLL Configuration (continued) RCWLR[COREPLL] core_clk : csb_clk Ratio VCO Divider 1 0–1 2–5 6 |
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