WM8952ECSSLASHRV datasheet(42/72 Pages) WOLFSON

42 / 72 page

WM8952

Pre Production

PP, Rev 3.1, June 2011

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master / slave mode are summarised

below.

and FRAME are outputs. The frequency of BCLK and FRAME in master mode are controlled with

BCLKDIV. These are divided down versions of master clock. This may result in short BCLK pulses

at the end of a frame if there is a non-integer ratio of BCLKs to FRAME clocks.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Audio interface

control

LOUTR

LOUTR control

0=normal

1=Input mono channel data output on

both left and right channels

BCP

BCLK polarity

0=normal

1=inverted

FRAMEP

Frame clock polarity (for RJ, LJ and I2S

formats)

0=normal

1=inverted

DSP Mode control

1 = Configures interface so that MSB is

available on 1st BCLK rising edge after

FRAME rising edge

0 = Configures interface so that MSB is

available on 2nd BCLK rising edge after

FRAME rising edge

6:5

Word length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits (see note)

4:3

FMT

Audio interface Data Format Select:

00=Right Justified

01=Left Justified

10=I2S format

11= DSP/PCM mode

ALRSWAP

Controls whether ADC data appears in

‘right’ or ‘left’ phases of FRAME clock:

0=ADC data appear in ‘left’ phase of

FRAME

1=ADC data appears in ‘right’ phase of

FRAME

Companding

Control

WL8

8 Bit Word Length Enable

Only recommended for use with

companding

0=Word Length controlled by WL

1=8 bits

Table 29 Audio Interface Control

Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected the

device will operate in 24-bit mode.

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