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WM8952ECS/RV Scheda tecnica(PDF) 58 Page - Wolfson Microelectronics plc

Il numero della parte WM8952ECS/RV
Spiegazioni elettronici  Mono ADC with Microphone Pre-amplifier
PDF  72 Pages
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Produttore elettronici  WOLFSON [Wolfson Microelectronics plc]
Homepage  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8952ECS/RV Scheda tecnica(HTML) 58 Page - Wolfson Microelectronics plc

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WM8952
Pre Production
w
PP, Rev 3.1, June 2011
58
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
7
FRAMEP
0
Frame clock polarity
0=normal
1=inverted
Digital Audio
Interfaces
DSP Mode control
1 = Configures the interface so that MSB is available
on 1st BCLK rising edge after FRAME rising edge
0 = Configures the interface so that MSB is available
on 2nd BCLK rising edge after FRAME rising edge
6:5
WL
10
Word length
00=16 bits
01=20 bits
10=24 bits
11=32 bits
Digital Audio
Interfaces
4:3
FMT
10
Audio interface Data Format Select:
00=Right Justified
01=Left Justified
10=I2S format
11= DSP/PCM mode
Digital Audio
Interfaces
2
0
Reserved
1
ALRSWAP
0
Controls whether ADC data appears in ‘right’ or ‘left’
phases of FRAME clock:
0=ADC data appear in ‘left’ phase of FRAME
1=ADC data appears in ‘right’ phase of FRAME
Digital Audio
Interfaces
0
0
Reserved
5 (05h)
15:6
000h
Reserved
5
WL8
0
8 Bit Word Length for companding
0=Word Length controlled by WL
1=8 bits
Digital Audio
Interfaces
4:3
Reserved
2:1
ADC_COMP
00
ADC companding
00=off
01=reserved
10=μ-law
11=A-law
Digital Audio
Interfaces
0
Reserved
6 (06h)
15:9
00h
Reserved
8
CLKSEL
1
Controls the source of the clock for all internal
operation:
0=MCLK
1=PLL output
Digital Audio
Interfaces
7:5
MCLKDIV
010
Sets the scaling for either the MCLK or PLL clock
output (under control of CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
Digital Audio
Interfaces



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